m52s32321a Elite Semiconductor Memory Technology Inc., m52s32321a Datasheet - Page 17
m52s32321a
Manufacturer Part Number
m52s32321a
Description
512k X 32bit X 2banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
1.M52S32321A.pdf
(29 pages)
- Current page: 17 of 29
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A10/AP
CLOCK
ADDR
ESMT
Page Write Cycle at Different Bank @Burst Length = 4
*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
Elite Semiconductor Memory Technology Inc.
CKE
DQM
RAS
CAS
WE
CS
DQ
BA
2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
0
Row Active
(A-Bank)
RAa
RAa
1
2
3
(A-Bank)
DAa0
Write
CAa
4
Row Active
(B-Bank)
RBb
DAa1
RBb
5
DAa2
6
DAa3
7
t
CDL
(B-Bank)
Write
DBb0
CBb
8
DBb1
9
DBb2 DBb3
HIGH
10
11
(A-Bank)
Write
DAc0
CAc
12
DAc1
13
(B-Bank)
DBd0
Write
CBd
14
Revision : 1.5
Publication Date : Jan. 2009
DBd1
M52S32321A
15
t
RDL
16
(Both Banks)
Precharge
*Note2
*Note1
17
18
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19
: Don't care
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