msx532 Fairchild Semiconductor, msx532 Datasheet
msx532
Related parts for msx532
msx532 Summary of contents
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... Dedicated RapidConfigure parallel interface or JTAG serial interface available for configuration and readback of MSX devices 3.3V operation, LVTTL I/O's (5V tolerant) MSX532 is offered in a 792 TBGA package Applications • Telecom and datacom switching • Video switches and servers • Test equipment Package Description ...
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... FIGURE 1. MSX532 Functional Block Diagram Introduction Switch Matrix The MSX family are SRAM-based, bit-oriented switching devices. The main functional block of the device is a Switch Matrix as shown in Figure 1. The Switch Matrix is an x-y routing structure (or grid). Each horizontal signal trace is hardwired to a corresponding vertical signal trace as shown by the junction dots ...
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... Next-Neighbor Clocking Included among the clocking options in MSX532 is the abil- ity to use an adjacent port as a clock source. This is referred Next-Neighbor Clock. In the MSX532, Port 0 can be clocked by Port 1, which can be clocked by Port 2, which can be clocked by Port 3, etc. In turn, Port 531 can be clocked by Port 0 ...
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Introduction (Continued) Option 1: Registered Input with Next-Neighbor Clock as Input Option 2: Registered Output with Next-Neighbor Clock as Input www.fairchildsemi.com 4 ...
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Introduction (Continued) Option 3: Registered Input with Next-Neighbor Clock as Output Option 4: Registered Output with Next-Neighbor Clock as Output 5 www.fairchildsemi.com ...
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Introduction (Continued) TABLE 1. Summary for Programmable I/O Attributes for MSX Devices Symbol Input Output Registered Input Registered Output Bidirectional Transceiver Bus Repeater Pin Side Force 0 Pin Side Force 1 No Connect Array Side Force 0 www.fairchildsemi.com I/O Port ...
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Introduction (Continued) Array Side Force 1 Bidirectional Transceiver with IE OE Register Input CLK Bidirectional Transceiver with IE Register Output CLK OE Bidirectional IE Transceiver Px Ax with ...
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... However, not all ports have access to the same global control sig- nals. There are four global clocks (CLK_0 through CLK_3), TABLE 2. MSX Global Control Signals MSX340 Port MSX532 Port Input/Output Number Number Clock Source 1 ...
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Introduction (Continued) RCI [1:0] Force Testing Command. Force commands can force a port to drive either a one or a zero to either the pad or 00 crosspoint array. These commands are generally only used for diagnostic testing. I/O Buffer ...
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Introduction (Continued) TABLE 5. I/O Buffer Read Commands Signal Description RCA[0] RCA[0] is set to one if the I/O buffer is an input zero if the I/O buffer is not configured as an input. Note that an I/O ...
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Introduction (Continued) Signal Description RCA[8] RCA[8] is set to a one if the I/O buffer is configured as a registered output and is assigned to use Next Neighbor Clocking zero if Next Neighbor Clocking is disabled. Next Neighbor ...
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Introduction (Continued) Crosspoint Programming Connections between ports through the crosspoint array can be quickly made or broken using the RC interface. The two ports to be connected or disconnected are addressed RCI[1:0] RCC[3: ...
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Introduction (Continued) TABLE 6. I/O Buffer Programming Commands Signal RCC[3] Bus Repeater Enable. Setting this bit to a one enables the I/O buffer to operate in Bus Repeater Mode, a special bi-directional mode. When zero the I/O buffer will not ...
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Introduction (Continued) Signal RCB[0] Inverted Output Clock. When this bit is set to a one, the registered output port’s selected clock source will be inverted. When zero the output clock source will not be inverted. JTAG Interface The dedicated JTAG ...
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Introduction (Continued) JTAG Architecture and Shift Registers FIGURE 5. MSX JTAG Architecture FIGURE 6. JTAG State Machine 15 www.fairchildsemi.com ...
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Introduction (Continued) Instruction Bit Number Bit Name Instruction Bypass Control Bit Buffer and Crosspoint Array ...
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... Introduction (Continued) Device Reset Options At power-on, all MSX532 I/O buffers are set as flow- through inputs (IN) with input enable ON, and the switch matrix set to all No Connects (NC). The RapidConfigure reset, hardware reset, and JTAG reset functions will program the I/O buffers to flow-through input (IN) mode with input enable ON, and each Loading SRAM cell in the Switch Matrix is set to No Connect ...
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... Description MSX532 Connected I/O’s P399-P531, P000-P132 P000-P132, P133-P265 P133-P265, P266-P398 P266-P398, P399-P531 MSX532 Connected I/O’s P399-P531, P000-P132 P000-P132, P133-P265 P133-P265, P266-P398 P266-P398, P399-P531 MSX532 Connected I/O’s P399-P531, P000-P132 P000-P132, P133-P265 P133-P265, P266-P398 P266-P398, P399-P531 RC Pins JTAG Pins Power and Ground Pins 18 ...
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Absolute Maximum Ratings Supply Voltage V DD Supply Voltage (Inputs (Note 6)(Note 7) Junction Temperature T J Storage Temperature T STG Maximum Power Dissipation P MAX Electrostatic Discharge ESD (Note 8) Pin Capacitance (Note 9) Symbol Parameter C ...
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AC Electrical Characteristics Symbol Parameter R NRZ Data Rate DATA f Registered Input/Output Clock Frequency RIO t Registered Clock Pulse Width, HIGH or LOW W_RIO t Registered Input Setup Time to Clock S_RI t Registered Output Setup Time to Clock ...
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Test Circuit and Timing Diagrams FIGURE 7. Test Circuit and Waveform Definition FIGURE 8. Registered Input and Registered Output Mode Timing (ICLK and OCLK Synchronized) FIGURE 9. Registered Input Timing Mode FIGURE 10. Registered Output Timing Mode 21 www.fairchildsemi.com ...
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Test Circuit and Timing Diagrams FIGURE 11. I/O Port Timing (Flow-through Mode) FIGURE 12. Input Enable Timing (Flow-through Mode) www.fairchildsemi.com (Continued) FIGURE 13. Output Enable Timing FIGURE 14. JTAG Timing 22 ...
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Test Circuit and Timing Diagrams FIGURE 15. RapidConfigure I/O Buffer or Crosspoint Read and Write Cycles (Continued) 23 www.fairchildsemi.com ...
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Test Circuit and Timing Diagrams RC_CLK RC_EN RC Read Cmd latched on RC_RDY falling edge of RC_CLK RCI[1:0] Reset Cmd Data RCC[3:0] Reset Cmd Data RCB[9:0] Cmd Data RCA[9:0] Cmd Data FIGURE 16. RapidConfigure Reset Command Cycle www.fairchildsemi.com (Continued) t ...
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... Package and Pinout MSX532 [792 TBGA Package] Pinout TRST P01 P03 Vss Vss Vss Vss # P00 P00 P02 Vss P016 Vss HW_RS P00 P01 P02 P03 Vss Vss CLK_ P00 ...
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... Package and Pinout (Continued) TABLE 10. MSX532 Pinout By Ball Sequence Ball Ball Name Ball Ball Name CLK_0 SS A5 TRST B5 HW_RST A6 P000 B6 P001 P002 SS A8 P007 B8 P006 A9 P012 B9 P013 A10 P016 B10 ...
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Package and Pinout (Continued) Ball Ball Name Ball Ball Name RCB7 SS G2 RCB3 H2 RCB6 G3 RCB2 H3 RCB5 G4 RCB0 H4 RCB4 G5 RCA9 RCA7 G34 P138 H34 ...
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Package and Pinout (Continued) Ball Ball Name Ball Ball Name AE1 V AF1 P458 SS AE2 P464 AF2 P459 AE3 P462 AF3 P457 AE4 P463 AF4 P456 AE5 P460 AF5 V DD AE6 P461 AF6 V DD AE34 P230 AF34 ...
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Package and Pinout (Continued) Ball Ball Name Ball Ball Name AP1 P424 AR1 V SS AP2 P422 AR2 P421 AP3 P420 AR3 P418 AP4 P419 AR4 V SS AP5 V AR5 AP6 V AR6 IE_3 DD AP7 ...
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... Package and Pinout (Continued) TABLE 11. MSX532 Pinout By Ball Name (alphabetically) Ball Name Ball Ball Name CLK_0 B4 P027 CLK_1 F37 P028 CLK_2 AW35 P029 CLK_3 AV4 P030 HW_RST B5 P031 IE_0 C5 P032 IE_1 D38 P033 IE_2 AP33 P034 IE_3 AR6 P035 OE_0 E6 P036 ...
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Ball Name Ball Ball Name Ball Ball Name P187 R39 P227 AD36 P188 T38 P228 AE36 P189 T37 P229 AE37 P190 U34 P230 AE34 P191 T39 P231 AE35 P192 U35 P232 AF39 P193 U36 P233 AF38 P194 U38 P234 AF36 ...
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Ball Name Ball Ball Name P387 AW11 P427 P388 AT11 P428 P389 AR11 P429 P390 AW10 P430 P391 AP11 P431 P392 AV10 P432 P393 AU10 P433 P394 AV9 P434 P395 AT10 P435 P396 AT9 P436 P397 AU9 P437 P398 AP9 ...
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Ball Name Ball Ball Name Ball Ball Name V F18 V AF6 F20 V AF34 F22 V AF35 F24 V AH5 F26 V AH6 F28 ...
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... Using the MSX532 with 10 Mb/s into a 10pF load with 266 inputs connected to 266 outputs: Power Consumption 252 mW + (0.006 266) + (0.013 x 266 10) 252 mW Example 2 Using the MSX532 with 150 Mb/s into a 10pF load with 266 inputs connected to 266 outputs: Power Consumption 252 mW + (0.006 x 150 x 266) + (0.013 x 266 x 150 x 10) 252 mW Glossary Array Side: The signal and connections between the Cros- spoint Array and the I/O Buffer ...
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Glossary (Continued) Extest: A JTAG instruction that samples I/O pin states and loads new I/O buffer states for testing device pin connec- tions. The MSX devices use a special test mode in Extext to observe the buffer data on the ...
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Physical Dimensions inches (millimeters) unless otherwise noted 792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch, 40mm Square Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...