msx532 Fairchild Semiconductor, msx532 Datasheet - Page 16

• Manufacturer Part Number: msx532
• Description: 532 Port Digital Crosspoint Switch With Lvttl I/o S
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Introduction
15 14 13 12
Bit Number
Bit Name
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1 Bypass
0 Control Bit
1 IO Buffer and
0 Device ID out
1 Set the JTAG Address
0 Access the Crosspoint Array
1 Disconnect a Port in the
0 Clear the Crosspoint Array
1 Shift the IO Buffer Data
0 Shift out the I/O buffer Copy
1 Access an I/O buffer
0
1 Test mode only
0 Crosspoint Array Write Testing,
0 Sample/Preload EXTEST
1 Sample/Preload EXTEST
Crosspoint Array Reset,
Device ID out
Register
and Update Array
Crosspoint Array
Register
Register
for programming device with
RapidConfigure through JTAG
Write one location per ShiftDR
15
13
(Continued)
Instruction
14
12
Instruction
13
11
12
10
C1
11
Control
TABLE 8. JTAG Input Format
TABLE 9. JTAG Instructions
Places device in a mode to pass TDI data to TDO with one clock delay. Used
for programming and testing devices through serial connected JTAG con-
trols.
Sets and clears the control bit A0 (LSB)
Resets I/O buffers for the Ports to Input and clear all Ports to Disconnect.
The device ID is serialized out to TDO. The Instruction serialized out is the
RESET Instruction during the Instruction phase. Update is forced to the cros-
spoint array
Serialize the device ID and revision history out to TDO. ID for the MSX is
0x0000A89F.
Set the 10-bit JTAG Address Register with the lower ten bits of the JTAG
Instruction Register. The lower ten bits of the JTAG Address Register
become the ’B’ Address for Crosspoint Access.
Read or Write the crosspoint addressed by the lower ten bits of the JTAG
Instruction (A Address) and the JTAG Address Register or Address Counter
(B Address). Read data is shifted out on TDO.
C1 C0 = 0 0 Read Switch with A and B Address.
Increment ’B’ address with each ShiftDR.
C1 C0 = 0 1 Connect switch at location Addressed with A and B.
Increment ’B’ address with each ShiftDR. Activate with UpdateDR.
C1 C0 = 1 0 Disconnect switch at location Addressed with A and B.
Increment ’B’ address with each ShiftDR. Activate with UpdateDR.
C1 C0 = 1 1 Force update of Switch Array Shadow register.
Activate with UpdateDR.
Disconnect all Ports from the Port Addressed by the lower ten bits of the
JTAG Instruction. The addressed port is reset to disconnect. The pro-
grammed state of the I/O buffer is not changed.
Clear the crosspoint array at no-connect. Leave the I/O buffers unchanged.
Shift twenty bits of data into and out of the I/O buffer Data register. The data
is used to program the I/O buffers. Parallel shift twenty bits into I/O buffer
Copy Register.
Shifts twenty bits of data out of the I/O buffer Copy Register. Data is either
the I/O buffer Data register shifted in by instruction 0111 or the last JTAG I/O
buffer Read Data.
Read or write the I/O buffer addressed with the lower ten bits of the JTAG
Instruction. Read data is placed in the twenty-bit I/O buffer Copy Register.
Write Data for the I/O buffer is from the I/O buffer Data Register.
C1 C0 = 0 0 Read an I/O buffer date into the Copy Register.
C1 C0 = 0 1 Write an I/O buffer with data in I/O buffer Data Register.
Not used.
Fairchild only - internal test mode to test RapidConfigure through JTAG.
Instruction Address = Lower Limit = A, Address Register = Upper Limit = B.
C1 = 1, C0 = 1 Connect all ports in address range
C1 = 1, C0 = 0 Connect Pattern=A[1] XOR B[1]
C1 = 0, C0 = 0 Connect Pattern=A[4]
C1 = 0, C0 = 1 Connect Pattern = NOT (A[1] XOR B[1]). Compliment
address limits, Address is complimented to test A-High Port to B-Low Port
connections. Other three patterns test opposite. The number of cycles =
(Sum of (X = 1), where X = Low Limit to X = High Limit) - 1
External scan tests for interconnect testing.
External scan tests for interconnect testing.
C0
10
A9
9
16
A8
8
A7
7
A6
6
Description
A5
Address
5
A4
4
A3
3
A2
2
A1
1
A0
0