msx532 Fairchild Semiconductor, msx532 Datasheet - Page 8

• Manufacturer Part Number: msx532
• Description: 532 Port Digital Crosspoint Switch With Lvttl I/o S
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Introduction
Control Signals
Every port on the MSX devices has two available global
clock inputs, input enables, and output enables. However,
not all ports have access to the same global control sig-
nals. There are four global clocks (CLK_0 through CLK_3),
RapidConfigure Interface
The MSX family of Digital Crosspoint Switches can be con-
figured in either of two ways. Both the JTAG serial pro-
gramming interface and the RapidConfigure (RC) parallel
interface can assign crosspoint connections and configure
I/O buffers, but JTAG is a serial input and is slower. JTAG
runs reliably up to 8 MHz and requires over twenty cycles
to program a single command. The RapidConfigure inter-
face can run at up to 40 MHz and can send a new com-
mand on every clock cycle. Systems requiring frequent
reconfiguration should be designed to use the RapidCon-
figure interface.
RapidConfigure is a 29 signal parallel interface that effec-
tively flattens the serial JTAG bitstream. Rather than con-
secutively shifting in twenty or so bits of data to configure
an I/O buffer or make a crosspoint connection, all of these
bits are driven on the RC lines simultaneously and then
latched in by the MSX device in a single cycle. Additionally,
the MSX RapidConfigure interface has been enhanced to
enable reading back of configuration data from the device.
Signal Description
The RC interface supports four types of operations. Two
are write operations to the MSX (I/O buffer configuration or
crosspoint programming) and two are read operations (I/O
buffer and crosspoint configuration read). The RC signals
serve different purposes depending upon the type of oper-
ation being performed.
Most of the signals on the MSX device’s RC interface are
bi-directional. These signals receive data during write oper-
ations. During read operations these pins receive data dur-
ing the first part of the cycle, and then drive the interface in
the final part of the cycle. RCA[9:0], RCB[9:0], and RCC[0]
are bi-directional pins. RCC[3:1], RC_CLK, RC_EN, and
RCA[9:0]
RCB[9:0]
RCC[3:0]
RCI[1:0]
RC_CLK
RC_EN
RC_RDY
Ports 0-84
Ports 85-169
Ports 170-254 Ports 266-398
Ports 255-339 Ports 399-531
MSX340 Port
Number
RapidConfigure Address A
RapidConfigure Address B
RapidConfigure Program Variable C
RapidConfigure Instruction Bits
RapidConfigure Clock
RapidConfigure Cycle Enable
Read out I/O buffer
and connect/disconnect status
Ports 0-132
Ports 133-265
MSX532 Port
(Continued)
Number
Clock Source 1
Input/Output
TABLE 2. MSX Global Control Signals
CLK_0
CLK_1
CLK_2
CLK_3
Clock Source 2
Input Output
CLK_1
CLK_2
CLK_3
CLK_0
8
four global input enables (IE_0 through IE_3), and four glo-
bal output enables (OE_0 through OE_3). Each global con-
trol signal is available to half of the ports on the MSX
device. Table 2 below shows the global control signals that
are available to each port.
RCI[1:0] are dedicated inputs. RC_RDY is a dedicated out-
put.
The RC_CLK signal is the strobe that latches write data
into the MSX device. It synchronizes the signals driven on
to the RC interface and determines the rate at which com-
mands can be loaded into the MSX device. The MSX
device latches command data on the falling edge of
RC_CLK when RC_EN is asserted. RC Write operations
can be repeated on consecutive clocks simply by keeping
the RC_EN signal asserted and providing new commands
on the RCA, RCB, RCC, and RCI signals. RC Read opera-
tions require four AC clock cycles and cannot be performed
on back-to-back clocks.
RC_EN is an Active LOW signal that enables an RC opera-
tion. Back-to-back RC Write operations may be performed
by keeping the RC_EN signal asserted. During RC Read
operations RC_EN must remain asserted until the cycle is
complete. Back-to-back RC Read operations can be exe-
cuted simply by keeping RC_EN asserted.
The MSX device asserts RC_RDY when it has entered the
final stage of a read and data out is ready. RC_RDY is
asserted on the falling edge of RC_CLK, and de-asserted
on the next falling edge. The MSX device will be driving
valid read data on the RC interface when RC_RDY is
asserted HIGH.
The RC interface specifies that the RCI signals be used to
determine the type of operation being performed.
FIGURE 4. MSX Switch Configuration Signals
Enable 1
Input
IE_0
IE_1
IE_2
IE_3
Enable 2
Input
IE_1
IE_2
IE_3
IE_0
Enable 1
Output
OE_0
OE_1
OE_2
OE_3
Enable 2
Output
OE_1
OE_2
OE_3
OE_0