lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 10

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

LRS1338A
Bus Operation
system. All bus cycles to or from the flash memory con-
form to standard microprocessor bus cycles.
READ
codes or status register independent of the V
age. RP can be either V
command (Read Array, Read Identifier Codes, or Read
Status Register) to the CUI. Upon initial device power-
up or after exit from deep power-down mode, the device
automatically resets to read array mode. Five control
pins dictate the data flow in and out of the component:
CE, OE, WE, RP and WP. CE and OE must be driven
active to obtain data at the outputs. CE is the device
selection control, and when active enables the selected
memory device. OE is the data output (I/O
trol and when active drives the selected memory data
onto the I/O bus. WE must be at V
V
OUTPUT DISABLE
puts are disabled. Output pins (I/O
in a HIGH impedance state.
STANDBY
standby mode which substantially reduces device
power consumption. I/O
a HIGH-impedance state independent of OE. If dese-
lected during block erase or word write, the device con-
tinues functioning, and consuming active power until
the operation completes.
DEEP POWER-DOWN
places output drivers in a HIGH-impedance state and
turns off all internal circuits. RP must be held LOW for
a minimum of 100 ns. Time t
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
will abort the operation. Memory contents being altered
are no longer valid; the data may be partially erased or
written. Time t
HIGH (V
10
IH
The local CPU reads and writes flash memory in-
Information can be read from any block, identifier
The first task is to write the appropriate read mode
With OE at a logic-HIGH level (V
CE at a logic HIGH level (V
RP at V
In read modes, RP-LOW deselects the memory,
During block erase or word write modes, RP-LOW
or V
HH
IH
) before another command can be written.
IL
. Figure 12 illustrates a read cycle.
initiates the deep power down mode.
PHWL
is required after RP goes to logic
IH
0
- I/O
or V
15
HH
IH
PHQV
) places the device in
outputs are placed in
.
IH
0
IH
and RP must be at
- I/O
), the device out-
is required after
15
0
) are placed
- I/O
PP
15
) con-
volt-
assert RP during system reset. When the system
comes out of reset, it expects to read from flash mem-
ory. Automated flash memories provide status informa-
tion when accessed during block erase or word write
modes. If a CPU reset occurs with no flash memory
reset, proper CPU initialization may not occur because
the flash memory may be providing status information
instead of array data. SHARP’s flash memories allow
proper CPU initialization following a system reset
through the use of RP input. In this application, RP is
controlled by the same RESET signal that resets the
system CPU.
READ IDENTIFIER CODES OPERATION
facturer code and device codes, the system CPU can
automatically match the device with its proper algorithms.
WRITE
device data and identifier codes. They also control
inspection and clearing of the status register.
tionally controls block erasure and word write. The
Block Erase command requires appropriate command
data and an address within the block to be erased. The
Word Write command requires the command and
address of the location to be written.
location. It is written when WE and CE are active. The
address and data needed to execute a command are
latched on the rising edge of WE or CE (whichever
goes HIGH first). Standard microprocessor write tim-
ings are used. Figure 13 and 14 illustrate WE and CE
controlled write operations.
As with any automated device, it is important to
The read identifier codes operation outputs the manu-
Figure 5. Device Identifier Code Memory Map
Writing commands to the CUI enable reading of
When V
The CUI does not occupy an addressable memory
7FFFF
00001
00000
CC
= V
Stacked Chip (8M Flash & 2M SRAM)
CC1
FUTURE IMPLEMENTATION
MANUFACTURER CODE
and V
RESERVED FOR
DEVICE CODE
PP
= V
PPH
, the CUI addi-
Data Sheet
1338A-5