lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 12

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

LRS1338A
READ ARRAY COMMAND
deep power-down mode, the device defaults to read
array mode. This operation is also initiated by writing
the Read Array command. The device remains
enabled for reads until another command is written.
Once the internal WSM has started a block erase or
word write, the device will not recognize the Read Array
command until the WSM completes its operation
unless the WSM is suspended via an Erase Suspend
or Word Write Suspend command. The Read Array
command functions independently of V
RP can be V
READ IDENTIFIER CODES COMMAND
Read Identifier Codes command. Following the com-
mand write, read cycles from addresses shown in Fig-
ure 5 retrieve the manufacturer and device codes (see
Table 7 for identifier code values). To terminate the
operation, write another valid command. Like the Read
Array command, the Read Identifier Codes command
functions independently of the V
be V
command, the following information can be read.
READ STATUS REGISTER COMMAND
a block erase or word write is complete and whether
the operation completed successfully. It may be read at
any time by writing the Read Status Register com-
mand. After writing this command, all subsequent read
operations output data from the status register until
another valid command is written. The status register
contents are latched on the falling edge of OE or CE,
whichever occurs. OE or CE must toggle to V
further reads to update the status register latch. The
Read Status Register command functions indepen-
dently of the V
12
Manufacture Code
Device Code (Top Boot)
Upon initial device power-up and after exit from
The identifier code operation is initiated by writing the
The status register may be read to determine when
IH
or V
CODE
HH
IH
Table 7. Identifier Codes
PP
. Following the Read Identifier Codes
or V
voltage. RP can be V
HH
.
ADDRESS
00000H
00001H
PP
voltage and RP can
IH
PP
or V
voltage and
00B0H
0060H
DATA
HH
IH
before
.
CLEAR STATUS REGISTER COMMAND
to ‘1’s by the WSM and can only be reset by the Clear
Status Register command. These bits indicate various
failure conditions (see Table x). By allowing system
software to reset these bits, several operations (such
as cumulatively erasing multiple blocks or writing sev-
eral words in sequence) may be performed. The status
register may be polled to determine if an error occurred
during the sequence.
ter command (50H) is written. It functions indepen-
dently of the applied V
V
erase or word write suspend modes.
BLOCK ERASE COMMAND
by a two-cycle command. A block erase setup is first
written, followed by a block erase confirm. This com-
mand sequence requires appropriate sequencing and
an address within the block to be erased (erase
changes all block data to FFFFH). Block precondition-
ing, erase, and verify are handled internally by the
WSM (invisible to the system). After the two-cycle block
erase sequence is written, the device automatically
outputs status register data when read (see Figure 6).
The CPU can detect block erase completion by analyz-
ing the output data of the status register bit SR.7.
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective action. The CUI
remains in read status register mode until a new com-
mand is issued.
lowed by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SR.5 being set to ‘1’. Also, reliable block erasure
can only occur when V
the absence of this high voltage, block contents are
protected against erasure. If block erase is attempted
while V
Successful block erase for boot blocks requires that if
set WP = V
to boot block when the corresponding WP = V
RP = V
operations with V
results and should not be attempted.
HH
Status register bits SR.5, SR.4, SR.3 or SR.1 are set
To clear the status register, the Clear Status Regis-
Erase is executed one block at a time and initiated
When the block erase is complete, status register bit
This two-step command sequence of set-up fol-
. This command is not functional during block
IH
PP
, SR.1 and SR.5 will be set to ‘1’. Block erase
IH
V
or RP = V
PPLK
Stacked Chip (8M Flash & 2M SRAM)
IH
, SR.3 and SR.5 will be set to ‘1’.
< RP < V
CC
PP
HH
. If block erase is attempted
= V
voltage. RP can be V
CC1
HH
and V
produce spurious
PP
Data Sheet
= V
PPH
IH
IL
. In
or
or