lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 9

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

Stacked Chip (8M Flash & 2M SRAM)
Principles of Operation
includes an on-chip WSM to manage block erase and
word write functions. It allows for: 100% TTL-level con-
trol inputs, fixed power supplies during block erasure,
word write, and minimal processor overhead with
RAM-like interface timings.
power-down mode (see ‘Bus Operation’), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
through the CUI independent of the F-V
High voltage on F-V
sure and word writing. All functions associated with
altering memory contents — block erase, word write,
status, and identifier codes — are accessed via the CUI
and verified through the status register.
sor write timings. The CUI contents serve as input to
the WSM, which controls the block erase and word
write. The internal algorithms are regulated by the
WSM including pulse repetition, internal verification,
and margining of data. Addresses and data are inter-
nally latched during write cycles. Writing the appropri-
ate command outputs array data, accesses the
identifier codes or outputs status register data.
block erase and word write can be stored in any block.
This code is copied to and executed from system RAM
during flash memory updates. After successful comple-
tion, reads are again possible via the Read Array com-
mand. Block erase suspend allows system software to
suspend a block erase to read/write data from/to blocks
other than that which is suspended. Word write sus-
pend allows system software to suspend a word write to
read data from any other flash memory array location.
DATA PROTECTION
may choose to make the V
(available only when memory block erases or word
writes are required) or hardwired to V
accommodates either design practice and encourages
optimization of the processor-memory interface.
Data Sheet
The LRS1388A SmartVoltage flash memory
After initial device power-up or return from deep
Status register and identifier codes can be accessed
Commands are written using standard microproces-
Interface software that initiates and polls progress of
Depending on the application, the system designer
PP
enables successful block era-
PP
power supply switchable
PPH
. The device
PP
voltage.
altered. The CUI, with two-step block erase or word
write command sequences, provides protection from
unwanted operations even when high voltage is
applied to V
V
RP is at V
ity for WP provides additional protection from inad-
vertent code or data alteration by block erase and
word write operations.
CC
When V
is below the write lockout voltage V
7DFFF
7CFFF
7FFFF
7EFFF
7BFFF
7AFFF
6FFFF
5FFFF
4FFFF
3FFFF
2FFFF
1FFFF
0FFFF
FE000
7D000
7C000
7B000
7A000
79FFF
78FFF
77FFF
67FFF
57FFF
47FFF
37FFF
27FFF
17FFF
07FFF
7F000
79000
78000
70000
68000
60000
58000
50000
48000
40000
38000
30000
28000
20000
18000
10000
08000
00000
IL
PP
. The device’s boot blocks locking capabil-
PP
. All write functions are disabled when
4K-WORD PARAMETER BLOCK
4K-WORD PARAMETER BLOCK
4K-WORD PARAMETER BLOCK
4K-WORD PARAMETER BLOCK
4K-WORD PARAMETER BLOCK
4K-WORD PARAMETER BLOCK
Figure 4. Memory Map
V
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
32K-WORD MAIN BLOCK
4K-WORD BOOT BLOCK
4K-WORD BOOT BLOCK
32K-WORD MAIN BLOCK
PPLK
, memory contents cannot be
TOP BOOT
LKO
LRS1338A
10
12
13
14
11
or when
LRS1338A-4
0
1
0
2
3
4
5
0
2
3
4
5
6
7
8
9
1
1
9