lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 8

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

LRS1338A
8
I/O
SYMBOL
A
0
0
GND
V
V
WE
WP
CE
RP
OE
- A
- I/O
CC
PP
18
15
Input/Output
Supply
Supply
Supply
TYPE
Input
Input
Input
Input
Input
Input
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during the write cycle.
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; out-
puts data during memory array, status register, and identifier code read cycles. Data
pins float to HIGH-impedance when the chip is deselected or outputs are disabled.
Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE-HIGH deselects the device and reduces power consumption
to standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and
resets internal automation. RP-HIGH enables normal operation. When driven
LOW, RP inhibits write operations which provides data protection during power
transitions. Exit from deep power-down sets the device to read array mode. With
RP = V
Block erase or word write with V
not be attempted.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CIU and array blocks. Addresses and data
are latched on the rising edge of the WE pulse.
WRITE PROTECT: Master control for boot blocks locking. When V
blocks cannot be erased and programmed.
BLOCK ERASE and WORD WRITE POWER SUPPLY: For erasing array blocks or
writing words. With V
and word write with an invalid V
results and should not be attempted.
DEVICE POWER SUPPLY: Do not float any power pins. With V
write attempts to the flash memory are inhibited. Device operations at invalid
V
be attempted.
GROUND: Do not float any ground pins.
CC
voltage (see ‘DC Characteristics’) produce spurious results and should not
HH
Table 4. Flash Pin Descriptions
, block erase or word write can operate to all blocks without WP state.
PP
V
PPLK
NAME AND FUNCTION
IH
PP
, memory contents cannot be altered. Block erase
< RP < V
(see ‘DC Characteristics’) produce spurious
HH
Stacked Chip (8M Flash & 2M SRAM)
produce spurious results and should
CC
IL
, locked boot
V
LKO
Data Sheet
, all