lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 14

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

LRS1338A
WORD WRITE COMMAND
sequence. Word write setup (standard 40H or alternate
10H) is written, followed by a second write that speci-
fies the address and data (latched on the rising edge of
WE). The WSM then takes over, controlling the word
write and write verify algorithms internally. After the
word write sequence is written, the device automati-
cally outputs status register data when read (see Fig-
ure 7). The CPU can detect the completion of the word
write event by analyzing the status register bit SR.7.
SR.4 should be checked. If word write error is detected,
the status register should be cleared. The internal
WSM verify only detects errors for ‘1’s that do not suc-
cessfully write to ‘0’s. The CUI remains in read status
register mode until it receives another command.
and V
memory contents are protected against word writes. If
word write is attempted while V
ter bits SR.3 and SR.4 will be set to ‘1’.
set, that WP = V
attempted to boot block when the corresponding WP =
V
write operations with V
results and should not be attempted.
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Word write is executed by a two-cycle command
When word write is complete, status register bit
Reliable word writes can only occur when V
Successful word write for boot blocks requires that if
or RP = V
PP
and V
IH
PPH
, SR.1 and SR.4 will be set to ‘1’. Word
. In the absence of this high voltage,
IH
or RP = V
IH
< RP < V
PP
HH
HH
V
. If word write is
PPLK
produce spurious
, status regis-
CC
= V
CC1
BLOCK ERASE SUSPEND COMMAND
erase interruption to read or word-write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests
that the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device out-
puts status register data when read after the Block
Erase Suspend command is written. Polling status reg-
ister bits SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be set
to ‘1’). Specification t
suspend latency.
to read data from blocks other than that which is sus-
pended. A Word Write command sequence can also be
issued during erase suspend to program data in other
blocks. using the Word Write Suspend command (see
‘Word Write Suspend Command’ section), a word write
operation can also be suspended. During a word write
operation with block erase suspended, status register
bit SR.7 will return to ‘0’. However, SR.6 will remain ‘1’
to indicate block erase suspend status.
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is
written to the flash memory, the WSM will continue the
block erase process. Status register bits SR.6 and
SR.7 will automatically clear. After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 8). V
must remain at V
block erase) while block erase is suspended. RP must
also remain at V
block erase). WP must also remain at V
same WP level used for block erase). Block erase can-
not resume until word write operations initiated during
block erase suspend have completed.
The Block Erase Suspend command allows block-
At this point, a Read Array command can be written
The only other valid commands while block erase is
Stacked Chip (8M Flash & 2M SRAM)
IH
PPH
or V
WHRH2
HH
(the same V
(the same RP level used for
defines the block erase
PP
level used for
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Data Sheet
or V
IH
(the
PP