lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 19

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

Stacked Chip (8M Flash & 2M SRAM)
Design Considerations
THREE-LINE OUTPUT CONTROL
arrays. SHARP provides three control inputs to accom-
modate multiple memory connections. Three-line con-
trol provides for:
• Lowest possible memory power dissipation.
• Complete assurance that data bus contention will
decoder should enable CE while OE should be con-
nected to all memory devices and the system’s READ
control line. This assures that only selected memory
devices have active outputs while deselected memory
devices are in standby mode. RP should be connected
to the system POWERGOOD signal to prevent unin-
tended writes during system power transitions. POW-
ERGOOD should also toggle during system reset.
POWER SUPPLY DECOUPLING
require careful device decoupling. System designers
are interested in three supply current issues: standby
current levels, active current levels and transient peaks
produced by falling and rising edges of CE and OE.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device should
have a 0.1 µF ceramic capacitor connected between its
V
high-frequency, low inductance capacitors should be
placed as close as possible to package leads. Addition-
ally, for every eight devices, a 4.7 µF electrolytic capac-
itor should be placed at the array’s power supply
connection between V
will overcome voltage slumps caused by PC board
trace inductance.
V
system requires that the printed circuit board designer
pay attention to the V
pin supplies the memory cell current for word writing
and block erasing. Use similar trace widths and layout
considerations given to the V
V
voltage spikes and overshoots.
V
V
side of a valid V
error is detected, status register bit SR.3 is set to ‘1’
Data Sheet
CC
PP
PP
CC
PP
not occur.
The device will often be used in large memory
To use these control inputs efficiently, an address
Flash memory power switching characteristics
Updating flash memories that reside in the target
Block erase and word write are not guaranteed if
, V
TRACE ON PRINTED CIRCUIT BOARDS
falls outside of a valid V
supply traces and decoupling will decrease V
and GND and between its V
PP
RP TRANSITIONS
CC1
range, or RP
PP
CC
power supply trace. The V
and GND. The bulk capacitor
PPH
CC
power bus. Adequate
range, V
PP
V
and GND. These
IH
or V
CC
HH
falls out-
. If V
PP
PP
PP
along with SR.4 or SR.5, depending on the attempted
operation. If RP transitions to V
word write, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP transitions to V
the status register.
ware and is not altered by V
WSM actions. Its state is read array mode upon power-
up, after exit from deep power-down or after V
sitions below V
nation down to V
array mode via the Read Array command if subsequent
access to the memory array is desired.
POWER-UP/DOWN PROTECTION
accidental block erasure or word writing during power
transitions. Upon power-up, the device is indifferent as
to which power supply (V
Internal circuitry resets the CUI to read array mode at
power-up.
writes for V
Since both WE and CE must be LOW for a command
write, driving either to V
two-step command sequence architecture provides
added level of protection against data alteration.
code or data alteration.
its control inputs state.
POWER DISSIPATION
consider battery power consumption not only during
device operation, but also for data retention during sys-
tem idle time. Flash memory’s non-volatility increases
usable battery life because data is retained when sys-
tem power is removed.
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can con-
sume negligible power by lowering RP to V
sleep modes. If access is again needed, the devices
can be read following the t
cycles required after RP is first raised to V
Characteristics — Read Only and Write Operations’
and Figure 12, 13 and 14 for more information.
The CIU latches commands issued by system soft-
After block erase or word write, even after V
The device is designed to offer protection against
A system designer must guard against spurious
WP provide additional protection from inadvertent
The device is disabled while RP = V
When designing portable systems, designers must
In addition, deep power-down mode ensures
CC
voltages above V
LKO
PPLK
.
, the CUI must be placed in read
HH
PP
will inhibit writes. The CUI’s
PHQV
or V
PP
IL
LKO
during block erase or
or CE transitions or
CC
and t
when V
) powers-up first.
IL
PHWL
regardless of
IL
PP
IH
LRS1338A
standby or
. See ‘AC
wake-up
is active.
CC
IL
PP
clear
tran-
tar-
19