gs8662d08bgd-333i GSI Technology, gs8662d08bgd-333i Datasheet

gs8662d08bgd-333i

Manufacturer Part Number

gs8662d08bgd-333i

Description

72mb Sigmaquad-ii Burst Of 4 Sram

Manufacturer

GSI Technology

Datasheet

1.GS8662D08BGD-333I.pdf (36 pages)

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165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 144 Mb devices

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaQuad™ Family Overview

The GS8662D08/09/18/36BD are built in compliance with

the SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662D08/09/18/36BD SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8662D08/09/18/36BD SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

Rev: 1.00 5/2010

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tKHKH

tKHQV

0.45 ns

3.0 ns

- 333

72Mb SigmaQuad-II

Burst of 4 SRAM

1/36

0.45 ns

3.3 ns

-300

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B4 RAMs always transfer

data in four packets, A0 and A1 are internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfers. Because the LSBs are tied off internally,

the address field of a SigmaQuad-II B4 RAM is always two

address pins less than the advertised index depth (e.g., the 4M

x 18 has a 1M addressable index).

0.45 ns

4.0 ns

-250

GS8662D08/09/18/36BD-333/300/250/200/167

0.45 ns

1 mm Bump Pitch, 11 x 15 Bump Array

5.0 ns

-200

165-Bump, 13 mm x 15 mm BGA

0.50 ns

6.0 ns

Bottom View

-167

1.8 V and 1.5 V I/O

333 MHz–167 MHz

Preliminary

1.8 V V

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