gs8662d08bgd-333i GSI Technology, gs8662d08bgd-333i Datasheet - Page 30

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gs8662d08bgd-333i

Manufacturer Part Number
gs8662d08bgd-333i
Description
72mb Sigmaquad-ii Burst Of 4 Sram
Manufacturer
GSI Technology
Datasheet
JTAG Port Recommended Operating Conditions and DC Characteristics
JTAG Port AC Test Conditions
Notes:
1.
2.
Rev: 1.00 5/2010
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Input Under/overshoot voltage must be –1 V < Vi < V
V
0 V ≤ V
Output Disable, V
The TDO output driver is served by the V
I
I
I
I
OHJ
OLJ
OHJC
OLJC
ILJ
Output reference level
Input reference level
= + 2 mA
= –2 mA
≤ V
= –100 uA
= +100 uA
Input high level
Input slew rate
Input low level
Parameter
IN
IN
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
≤ V
≤ V
Test Port Output High Voltage
ILJn
TDO Output Leakage Current
DDn
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
Test Port Input High Voltage
Test Port Input Low Voltage
OUT
= 0 to V
Parameter
DDn
DD
Conditions
supply.
V
DD
1 V/ns
V
0.2 V
V
DD
DD
– 0.2 V
/2
/2
DDn
30/36
+1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC.
Symbol
V
V
V
V
I
V
I
V
I
INHJ
OHJC
INLJ
OLJC
OLJ
GS8662D08/09/18/36BD-333/300/250/200/167
OHJ
OLJ
IHJ
ILJ
TDO
V
V
0.7 * V
DD
DD
Min.
–300
–0.3
–1
–1
– 0.2
– 0.1
DD
* Distributed Test Jig Capacitance
JTAG Port AC Test Load
0.3 * V
V
V
Max.
DD
DD
100
0.2
0.1
1
1
/2
+0.3
DD
50Ω
© 2010, GSI Technology
Preliminary
Unit Notes
uA
uA
uA
V
V
V
V
V
V
30pF
*
5, 6
5, 7
5, 8
5, 9
1
1
2
3
4

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