gs8662d08bgd-333i GSI Technology, gs8662d08bgd-333i Datasheet - Page 10

• Manufacturer Part Number: gs8662d08bgd-333i
• Description: 72mb Sigmaquad-ii Burst Of 4 Sram
• Manufacturer: GSI Technology

Example x18 RAM Write Sequence using Byte Write Enables
Resulting Write Operation
Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
Rev: 1.00 5/2010
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Data In Sample Time
D0–D8
Byte 1
Written
Beat 1
Beat 2
Beat 3
Beat 4
Beat 1
Unchanged
D9–D17
Byte 2
BW0
0
1
0
1
Unchanged
D0–D8
Byte 1
BW1
1
0
0
0
Beat 2
D9–D17
Byte 2
Written
10/36
Don’t Care
Don’t Care
D0–D8
Data In
Data In
D0–D8
Byte 1
GS8662D08/09/18/36BD-333/300/250/200/167
Written
Beat 3
D9–D17
Byte 2
Written
Don’t Care
D9–D17
Data In
Data In
Data In
Unchanged
D0–D8
Byte 1
© 2010, GSI Technology
Beat 4
Preliminary
D9–D17
Byte 2
Written