gs8662d08bgd-333i GSI Technology, gs8662d08bgd-333i Datasheet - Page 26

• Manufacturer Part Number: gs8662d08bgd-333i
• Description: 72mb Sigmaquad-ii Burst Of 4 Sram
• Manufacturer: GSI Technology

Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.00 5/2010
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TDI
TMS
TCK
·
·
·
·
Test Access Port (TAP) Controller
Bypass Register
Instruction Register
ID Code Register
31 30 29
2
0
JTAG TAP Block Diagram
Boundary Scan Register
·
1
0
Control Signals
26/36
·
·
· · ·
·
2
1
GS8662D08/09/18/36BD-333/300/250/200/167
0
·
·
·
·
TDO
© 2010, GSI Technology
Preliminary