gs8662d08bgd-333i GSI Technology, gs8662d08bgd-333i Datasheet - Page 9

• Manufacturer Part Number: gs8662d08bgd-333i
• Description: 72mb Sigmaquad-ii Burst Of 4 Sram
• Manufacturer: GSI Technology

Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Note:
If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 ns to reset the DLL after the
clocks become stablized.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.
Rev: 1.00 5/2010
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Power-Up Sequence
DLL Constraints
1. Power-up and maintain Doff at low state.
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t
• The DLL cannot operate at a frequency lower than that specified by the t
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause
table).
operating clock frequency.
undefined errors or failures during the initial stage.
1a. Apply V
1b. Apply V
1c. Apply V
DD
DDQ
REF
.
(may also be applied at the same time as V
.
9/36
GS8662D08/09/18/36BD-333/300/250/200/167
DDQ
).
KHKH
maximum specification for the desired
KCVar
in AC Characteristics
© 2010, GSI Technology
Preliminary