cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 139

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x2C—TXCELLINT (Transmit Cell Interrupt Indication Status Register)
ParErrInt
SOCErrInt
TxOvflInt
RxOvflInt
CellSentInt
BusCnflctInt
0x2D—RXCELLINT (Receive Cell Interrupt Indication Status Register)
LOCDInt
HECDetInt
HECCorrInt
CellRcvdInt
IdleRcvdInt
NonMatchInt
NonZerGFCInt
500028C
ParErrInt
LOCDInt
7
7
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(1)
(2)
(2)
(1)
(2)
(2)
SOCErrInt
HECDetInt
When a logical 1 is read, this bit indicates that a Parity Error occurred.
When a logical 1 is read, this bit indicates that a Start of Cell Error occurred.
When a logical 1 is read, this bit indicates that a Transmit FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a Receive FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a cell has been sent.
When a logical 1 is read, this bit indicates that a Bus Conflict occurred.
When a logical 1 is read, this bit indicates that a Loss of Cell Delineation has occurred.
When a logical 1 is read, this bit indicates that a HEC Error was detected.
When a logical 1 is read, this bit indicates that a HEC Error was corrected.
When a logical 1 is read, this bit indicates that a cell has been received.
When a logical 1 is read, this bit indicates that an Idle Cell has been received.
When a logical 1 is read, this bit indicates that a Non-matching Cell has been received.
When a logical 1 is read, this bit indicates that a Non-zero GFC has been received.
6
6
The TXCELLINT register indicates that a change of status has occurred within the
Transmit Status signals.
The RXCELLINT register indicates that a change of status has occurred within the
Receive Status signals.
NOTE:
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
HECCorrInt
TxOvflInt
5
5
Mindspeed Technologies™
(1)
interrupt to occur, provided that this interrupt has been enabled by the corresponding
enable bit. Reading this interrupt register clears this interrupt.
(1)
causes this interrupt to occur, provided that this interrupt has been enabled by the
corresponding enable bit. Reading this interrupt register clears this interrupt.
(2)
interrupt to occur, provided that this interrupt has been enabled by the corresponding
enable bit. Reading this interrupt register clears this interrupt.
Single event—A 0 to 1 transition on the corresponding status bit causes this
Dual event—Either a 0 to 1 or a 1 to 0 transition on the corresponding status bit
Single event—A 0 to 1 transition on the corresponding status bit causes this
RxOvflInt
—
4
4
CellRcvdInt
CellSentInt
3
3
BusCnflctInt
IdleRcvdInt
2
2
NonMatchInt
—
1
1
NonZerGFCInt
—
0
0
Registers
3
-
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