cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 30

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Product Description
Table 1-4. Hardware Signal Definition, ATM UTOPIA Interface (1 of 2)
1-16
UTxCLK
UTxENB*
UTxAddr[0]
UTxAddr[1]
UTxAddr[2]
UTxAddr[3]
UTxAddr[4]
UTxData[0]
UTxData[1]
UTxData[2]
UTxData[3]
UTxData[4]
UTxData[5]
UTxData[6]
UTxData[7]
UTxData[8]
UTxData[9]
UTxData[10]
UTxData[11]
UTxData[12]
UTxData[13]
UTxData[14]
UTxData[15]
UTxPrty
UTxSOC
UTxCLAV
URxCLK
URxENB*
Label
Pin
UTOPIA Transmit
Clock
Transmit Enable
UTOPIA Transmit
Address
UTOPIA Transmit Data
UTOPIA Transmit
Parity Input
UTOPIA Transmit
Start of Cell
UTOPIA Transmit
Cell Available
UTOPIA Receive Clock
Receive Enable
Signal
Name
Preliminary Information/Mindspeed Proprietary and Confidential
CX28365
Pin#
M26
D25
H24
K25
K26
G24
H25
H26
G25
D22
G26
D24
C23
D26
C26
D21
C25
L25
L26
J25
J26
F24
E24
F25
F26
E25
E26
C22
Mindspeed Technologies™
CX28366
Pin#
M26
D25
C25
H24
K25
K26
G24
H25
H26
G25
D22
G26
D24
C23
D26
C26
C22
D21
L25
L26
J25
J26
F24
E24
F25
F26
E25
E26
CX28364
Pin#
M26
D25
C25
L25
H24
L26
K25
K26
G24
H25
H26
G25
E24
D22
G26
D24
E25
C23
D26
E26
C26
C22
D21
J25
J26
F24
F25
F26
I/O
O
I
I
I
I
I
I
I
I
Clock input used to synchronize
transmitted data. Schmitt trigger input.
Enables data transmission when asserted
low. Schmitt trigger input.
Address of the PHY device being selected
for transmission. Address 1111 (31
decimal) indicates a null PHY port.
Schmitt trigger input.
Transmit data from the ATM layer.
Schmitt trigger input.
Parity calculated over the UTxData bus.
BusWidth (bit 0) in the IOMODE register
(0x0202) determines whether parity is
checked over UTxData[7:0] or
UTxData[15:0]. OddEven (bit 2) in the
UTOP1 register (0x0D) determines
whether this pin represents even or odd
parity. Schmitt trigger input.
Indicates the first byte of valid cell data
transmitted when asserted high. Schmitt
trigger input.
Indicates a FIFO full condition or Cell
Available condition, depending upon
UTOPIA HandShake (bit 1) in the
SYSBUS register (0xE01). An external
pulldown resistor is required for this pin.
Clock input used to synchronize received
data. Schmitt trigger input.
Enables data reception when asserted
low. Schmitt trigger input.
Definition
CX28365/6/4 Data Sheet
500028C