cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 57

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.1.1.5
500028C
Terminal Data Link Transmission
A terminal data link channel can be implemented over the 3 C-bits in subframe 5 in
DS3, C-bit parity mode, over the N-bit in E3-G.751 mode, and over GC byte or the
NR byte in E3-G.832 mode of operation (either GC or NR not both).
The transmitted data link bits for each mode of operation can be supplied to the
transmitter circuit externally via the data stream or on TEXTI (external overhead input
pin). They can be processed internally using an internal FIFO buffer, which is
accessed via a microprocessor-controlled interface. When the data link is disabled and
its bits are not supplied externally, the transmitter circuit automatically inserts a
default value to the transmitted data link bits: i.e., in DS3 C-bit parity mode, the 3 C-
bits in subframe 5 are transmitted as 1; in E3-G.751 mode, N-bit is transmitted as 1;
and in E3-G.832 when the data link is disabled on NR or GC (or both), those bytes are
transmitted as 1.
The following sections describe the transmit side terminal data link implementation
using an internal FIFO buffer. Setting bits DLMod[2:0] in the Transmit Overhead
Insertion 1 Control register Feature Control registers, can enable this mode for each
rate.
For this mode of operation, the framer is controlled internally by a FIFO buffer and
LAPD/HDLC formatting circuitry to implement a LAPD/HDLC terminal data link
transmission according to ITU-T Q.921 and ISO/IEC 3309 standards.
HDLC/LAPD Formatting Circuitry
The HDLC/LAPD formatting circuitry includes the following:
The formatting circuitry has the capability of calculating the 16-bit Frame Check
Sequence (FCS) and transmitting it at the end of the message. Transmitting of FCS is
software-selectable by the settings of TxFCSEn in the Transmit Data Link Control
register.
FIFO Buffer Control Circuitry
The transmit data link side (TDL) of each framer includes a 128-byte FIFO buffer that
is additional to a 128-byte receiver-side data link FIFO buffer (RDL). The FIFO
buffer is filled by the microprocessor with the data bytes to be transmitted for each
message, and also provides interrupts and status bits to indicate its condition.
Writing to the FIFO Buffer
The FIFO buffer is written using the microprocessor interface. Writing a byte each
time to the Transmit Data Link Message Byte register (TxDLMsg [7:0] byte) fills the
FIFO buffer with a new message. The writing of the message byte adds it to the FIFO
buffer.
The Transmit Data Link Message Byte register has two addresses. The low address is
used to write all message bytes except the last byte; the high address is used to write
Preliminary Information/Mindspeed Proprietary and Confidential
Automatic generation of FLAG sequences (01111110) when no message is being
transmitted and between messages
Zero insertion mechanism for transparency (a 0 bit is inserted after all sequences
of five continuous 1 bits in a message between two FLAGs including the FCS to
differ data from FLAG transmission)
Automatic generation of abort sequence (a sequence of 16 continuous 1 bits)
Mindspeed Technologies™
Functional Description
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