cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 167

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
0x2F—CR15 (Transmit Data Link Message Byte, Low Address)
0x30—CR15 (Transmit Data Link Message Byte, High Address)
TxDLMsg [7:0]
500028C
TxDLMsg[7]
7
TxDLMsg[6]
Transmit Data Link Message Byte—This byte is loaded with data to be written into the Data
Link FIFO buffer, which is later transmitted by the Data Link Transmitter circuit. Two
addresses are allocated for this register. During the whole message, except the last byte, the
lower address is used to access this register. When the last byte of the message is written to this
register, the higher address is used. The higher address indicates the end of the message to the
transmitter circuit. TxDLMsg [0] bit is transmitted first and TxDLMsg [7] bit is transmitted
last. Reading this register causes latching of the content of the FIFO stage pointed by the
Transmit Data Link Read pointer into this register.
6
Default after reset: Undefined
Direction: Read/Write
Modification: Dynamic
Preliminary Information/Mindspeed Proprietary and Confidential
TxDLMsg[5]
5
Mindspeed Technologies™
TxDLMsg[4]
4
TxDLMsg[3]
3
TxDLMsg[2]
2
TxDLMsg[1]
1
TxDLMsg[0]
0
Registers
3
-
57