cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 37
cx28365
Manufacturer Part Number
cx28365
Description
X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28365.pdf
(228 pages)
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CX28365/6/4 Data Sheet
Table 1-7. Hardware Signal Definition, Test, and Control (1 of 2)
500028C
TRST*
TCK
TMS
TDI
TDO
TESTMOD[2]
TESTMOD[1]
TESTMOD[0]
OutDis
NC, NB
Label
Pin
JTAG Test Reset
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Test mode control
Output Disable Control
Spare
Signal
Name
Preliminary Information/Mindspeed Proprietary and Confidential
CX28365
A25
A20
A22
A21
A19
Y4
V4
T4
U23
AC8,
AD7, AE4,
AE5,
AE23,
AF2,
AF23,
AF24
Pin#
Mindspeed Technologies™
CX28366
A25
A20
A22
A21
A19
Y4
V4
T4
U23
AC8,
AD7, AE4,
AE5,
AE23,
AF2,
AF23,
AF24
Pin#
A25
A20
A22
A21
A19
Y4
V4
T4
U23
AC8,
AD7, AE4,
AE5,
AE23,
AF2,
AF23,
AF24
CX28364
Pin#
I/O
—
I
I
I
I
I
I
I
When this pin is asserted, the internal
boundary-scan logic is reset. This pin is
internally pulled high.
Samples the value of TMS and TDI on its
rising edge in order to control the boundary
scan operations (input clock).
Controls the boundary-scan Test Access
Port (TAP) controller operation. This pin is
internally pulled high.
Controls the boundary-scan Test Access
Port (TAP) controller operation. This pin is
internally pulled high.
Serial test data output.
Activates test modes. Factory use only.
These pin must be connected to ground for
normal operation.
When asserted high, all output pins are put
into high impedance, three-state mode.
Not connected, not bonded.
Definition
Product Description
1
-
23
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