cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 59

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
500028C
Set the desired interrupt settings for the Near-Empty FIFO threshold and the
TDL-related options to the desired values through the Transmit Data Link and the
Transmit Data Link Threshold Control registers. The insertion of the FCS is
software-selectable by setting the TxFCSEn field of the Transmit Data Link Control
register.
When only the Data Link is disabled, the FIFO buffer is cleared, and the Near-Empty
and Empty status bits are read. If the Near-Empty interrupt is enabled, a Near-Empty
interrupt is generated. Before disabling the Data Link, the user should mask its
interrupts. If the channel is enabled when disabling the Data Link a repetitive 1s signal
is sent. While the Data Link is disabled, the FIFO buffer can still be written.
When both the Data Link and the channel are enabled, if the FIFO buffer is not reset
and is not empty, a new message starts after sending two FLAG sequences. If the
FIFO buffer is empty, FLAG sequences are automatically transmitted until a new
message byte is written to the FIFO buffer.
When the entire channel is enabled after reset or disabled (while data link is enabled),
the FIFO buffer is cleared, the Near-Empty and Empty status bits are cleared, and if
the Near-Empty interrupt is enabled, a Near-Empty interrupt is generated.
When the whole channel is disabled, the following occurs:
Sending Message Using the FIFO—Normal Operation
In normal operation, when the TDL FIFO buffer is empty, the TDL circuitry generates
IDLE flags. When the system has a message to transmit on the data link, it must write
it to the FIFO buffer, one byte each time, by writing all data bytes (except the last
message byte) to the low address of the Transmit Data Link Message Byte register
(TxDLMsg[7:0]). The last byte of the message must be written to the high address of
the Transmit Data Link Message Byte register indicating to the TDL circuit that it is
the last byte of the message (EOM byte). After EOM, if the FIFO buffer is not FULL,
another message can be written following the last EOM byte.
There is no limit to the length of each message, and the FIFO buffer can contain more
than one message written to it at a time.
EMPTY and FULL status bits are provided to help the system evaluate the FIFO
buffer’s content, and message transmission status, Near-Empty Threshold and Status,
Transmitted Message Status indication and interrupt. With the help of these data bits,
the system can TDL FIFO buffer accesses.
The internal logic terminates sending FLAG messages as soon as a new message byte
is written to the FIFO buffer. The new message is sent until an EOM byte is
encountered, which is followed by sending FCS (if enabled) and two FLAG
sequences. After sending the closing FLAG of each message, an indication of
transmitted message and an interrupt (if enabled) is provided. The next message
Preliminary Information/Mindspeed Proprietary and Confidential
Data Link activities are terminated.
Data link control settings at the Transmit Data Link and the Transmit Data Link
Threshold Control registers are not affected (interrupt enables, Near-Empty
threshold, FCS transmission, etc.).
The channel’s old status at the Transmit Data Link FEAC Status register is
maintained (status bits maintain their old values and so do interrupts if not
disabled earlier).
The FIFO buffer is not emptied.
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Functional Description
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