cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 196

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Registers
Out1Mode[1:0]
Out2Mode
PortReset
0xE90–0xE9B—PORTINTn (Port N Interrupt Control/Status Register)
FrmrIntEn
CDIntEn
LIntEn
FrmChnEn
FrmrInt
CDInt
LInt
3-86
FrmrIntEn
7
These bits control the OUTPORT1 pin for the slice. The following status is placed on the
output pin:
00 = LOCD (or PLCP LOF) from cell delineator
01 = OOF from line framer
10 = Yellow alarm from line framer
11 = Bit ‘n’ from OUTPORT1 control register
This bit controls the OUTPORT2 pin for the slice. When set to 0, the external chip select
signal for port ‘n’ is placed on the output pin. When set to 1, bit ‘n’ from the OUTPORT2
control register is placed on the output pin.
When written to a logical 1, cell delineator device logic functions (for the appropriate port) are
held in reset mode.
When set to 1, the interrupts from the framer block for this port are enabled to appear on the
MINTR* pin.
When set to 1, the interrupts from the cell delineation block for this port are enabled to appear
on the MINTR* pin.
When set to 1, the line interrupt from the INPORT1 input for this port is enabled to appear on
the MINTR* pin.
Framer channel enable. Set to 1 for normal operation. Set to 0 to allow programming of framer
static controls.
This bit indicates that an interrupt has occurred in the framer block for this port.
This bit indicates that an interrupt has occurred in the cell delineation block for this port.
This bit indicates that an interrupt has occurred on the LInt* input for this port.
CDIntEn
6
Value after reset: 0000 xxxx
Direction: Read/Write
Preliminary Information/Mindspeed Proprietary and Confidential
LIntEn
5
Mindspeed Technologies™
FrmChnEn
4
FrmrInt
3
CDInt
2
LInt
1
CX28365/6/4 Data Sheet
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500028C