cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 97

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

CX28365/6/4 Data Sheet
2.4
2.4.1
2.4.1.1
Table 2-14. Reset Control
500028C
MReset* pin
GLOB[MasterReset]
GLOB[DevLogReset]
PMODE[PrtMstRst]
PORTn[PortReset]
Reset
Interfacing
Microprocessor Interface
Cell Delineator
The microprocessor interface transfers control and status information in 8-bit data
transfers between the external microprocessor and CX2836x by means of write and
read access to internal registers. This interface allows the microprocessor to configure
the CX2836x by writing various control registers. These control registers can also be
read for configuration confirmation. This interface also provides the ability to read
the device’s current condition via its status registers and counters. Summary status is
available for rapid interrupt identification.
The MPU interface consists of the following pins: MCs*, MOE*, MR/W*,
MData[7:0], MAddr[13:0], MINTR*, MReset*, 8KHZIn, OneSecIn, OneSecOut, and
MCLK. A detailed description of the MPU pins is provided in
Resets
Software Reset
There are four register controlled reset functions, two at the device level and two at the
port level. The two levels allow a user to reset either the entire CX2836x with one
command or only a port within the device. The two logic resets allow the user to keep
the device or port in a reset state while the control registers are being programmed.
When the reset bit is de-asserted, all changes to the registers take place simultaneously.
At the device level, the register bit GLOB[MasterReset] restarts all device logic
functions and sets the control and status registers to their default values. The
GLOB[DevLogReset] bit restarts cell delineator device logic functions but leaves all
control registers unaffected.
At the port level, the PMODE[PrtMstRst] bit restarts cell delineator port logic functions
and sets the cell delineator port registers to their default values. The PORTn[PortReset]
bit restarts cell delineator functions but leaves the control registers unaffected.
Hardware Reset
MReset* is an active low, level activated, synchronous reset pin. While MReset* is
active, RxCKI and TxCKI on all ports must be present for a minimum of 30 clock
cycles. During MReset* the system side outputs are high impedance, 3-state. After
MReset*, all ports are disabled and all control registers and counters are set to their
default values.
Logic
X
X
Preliminary Information/Mindspeed Proprietary and Confidential
X
X
X
Mindspeed Technologies™
Register Defaults
Delineator
Set Cell
—
—
X
X
X
Table 2-14
Framer Logic
summarizes the effect of each reset source.
—
—
—
X
X
Set Framer
Register
Defaults
—
—
—
X
X
Table
1-1.
Functional Description
Set Global
Register
Defaults
—
—
—
X
X
2
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