cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 141
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cx28365
Manufacturer Part Number
cx28365
Description
X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28365.pdf
(228 pages)
- Current page: 141 of 228
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CX28365/6/4 Data Sheet
0x2F—RXCELL (Receive Cell Status Register)
LOCD
HECDet
HECCorr
CellRcvd
IdleRcvd
NonMatch
NonZerGFC
500028C
LOCD
(1)
(2)
7
(2)
(2)
(2)
(2)
(2)
When a logical 1 is read, this bit indicates a Loss of Cell Delineation.
When a logical 1 is read, this bit indicates that an uncorrected HEC Error was detected.
When a logical 1 is read, this bit indicates that a HEC Error was corrected.
When a logical 1 is read, this bit indicates that a cell with a header matching the receive header
value and mask criteria was received.
When a logical 1 is read, this bit indicates that a cell with a header matching the receive idle
cell header value and mask criteria was received.
When a logical 1 is read, this bit indicates that a cell with a header not matching either the
receive cell or idle cell criteria was received.
When a logical 1 is read, this bit indicates that a cell with a Non-zero GFC field in the header
was received.
HECDet
6
The RXCELL register contains status for the cell receiver.
NOTE:
Preliminary Information/Mindspeed Proprietary and Confidential
HECCorr
5
Mindspeed Technologies™
(1)
(2)
This status reflects the current state of the circuit.
This status indicates an event that occurred since the register was last read.
—
4
CellRcvd
3
IdleRcvd
2
NonMatch
1
NonZerGFC
0
Registers
3
-
31
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