ST10 STMICROELECTRONICS [STMicroelectronics], ST10 Datasheet - Page 16

• Manufacturer Part Number: ST10
• Description: 16-BIT MCU WITH 32K BYTE ROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10C167
VII - INTERRUPT SYSTEM (continued)
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a stan-
dard interrupt service (branching to a dedicated
vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag regis-
Table 3 : Exceptions or error conditions that can arise during run time
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Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access
Reserved
Software Traps
TRAP Instruction
Exception Condit ion
UNDOPC
PRTFLT
STKOF
ILLOPA
ILLBUS
STKUF
ILLINA
Trap
Flag
NMI
STOTRAP
STUTRAP
NMITRAP
RESET
RESET
RESET
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
Vector
Trap
Any [00’0000h– 00’01FCh]
ter (TFR). Except when another higher prioritized
trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn,
hardware trap services can normally not be inter-
rupted by standard or PEC interrupts.
Table 3 shows all of the possible exceptions or
error conditions that can arise during run-time:
in steps of 4h
[2Ch –3Ch]
Location
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
Vector
[0Bh – 0Fh]
[00h – 7Fh]
Number
Trap
0Ah
0Ah
0Ah
0Ah
0Ah
Any
00h
00h
00h
02h
04h
06h
Current CPU
Priority
Priority
Trap
III
III
III
II
II
II
I
I
I
I
I