ST10 STMICROELECTRONICS [STMicroelectronics], ST10 Datasheet - Page 29

• Manufacturer Part Number: ST10
• Description: 16-BIT MCU WITH 32K BYTE ROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

XVII - SYSTEM RESET
The internal system reset function is invoked
either by asserting a hardware reset signal on pin
RSTIN (Hardware Reset Input), by the execution
of the SRST instruction (Software Reset) or by an
overflow of the watchdog timer. Whenever one of
these conditions occurs, the microcontroller is
reset into its predefined default state. The
following type of reset are implemented on the
ST10C167:
Asynchronous hardware reset
Asynchronous reset does not require a stabilized
clock signal on XTAL1, as it is not internally resyn-
chronized. It immediately resets the microcontrol-
ler into its default reset state.
This asynchronous reset is required upon
power-up of the chip and may be used during cat-
astrophic situations. The rising edge of the RSTIN
pin is internally resynchronized before exiting the
reset condition. Therefore, only the entry of this
hardware reset is asynchronous.
Synchronous hardware reset (warm reset)
A warm synchronous hardware reset is triggered
when the reset input signal RSTIN is latched low
and RPD (Pin 84) is high. The I/Os are
immediately
impedance, RSTOUT is driven low. After negation
of RSTIN is detected, a short transition period
elapses, during which pending internal hold states
are cancelled and any current internal access
cycles are completed, external bus cycles are
aborted.
Then, the internal reset sequence starts for 1024
TCL (512 CPU clock cycles). During this reset
sequence, if bit BDRSTEN was previously set by
software (bit 5 in SYSCON register), RSTIN pin is
driven low and internal reset signal is asserted to
reset the microcontroller in its default state. Note
that after all reset sequences, bit BDRSTEN is
cleared.
After the reset sequence has been completed, the
RSTIN input is sampled. If the reset input signal is
(asynchronously)
set
in
high
active at that time the internal reset condition is
prolonged until RSTIN becomes inactive.
Software reset
The reset sequence can be triggered at any time
by the protected instruction SRST (software
reset).
deliberately within a program, e.g. to leave
bootstrap loader mode, or on a hardware trap that
reveals a system failure. As for a synchronous
hardware reset, the reset sequence lasts 1024
TCL (512 CPU clock cycles), and drives the
RSTIN pin low.
Watchdog timer reset
When the watchdog timer is not disabled during
the initialization or serviced regularly during
program execution it will overflow and trigger the
reset sequence.
Unlike hardware and software resets, the watch-
dog reset completes a running external bus cycle
if this bus cycle either does not use READY, or if
READY is sampled active (low) after the pro-
grammed waitstates.
When READY is sampled inactive (high) after the
programmed waitstates the running external bus
cycle is aborted. The internal reset sequence is
then started. The watchdog reset cannot occur
while the ST10C167 is in bootstrap loader mode.
Bidirectional reset
This feature is enabled by bit 3 of the SYSCON
register. The bidirectional reset makes the watch-
dog timer reset and software reset externally visi-
ble. It is active for the duration of an internal reset
sequences caused by a watchdog timer reset and
software reset.
This means that the bidirectional reset transforms
an internal watchdog timer reset or software reset
into an external hardware reset with a minimum
duration of 1024 TCL. The consequence is that
during a watchdog timer reset or software reset,
the behavior of the ST10C167 is equal to an
external hardware reset.
This
instruction
can
be
ST10C167
executed
29/65