ST10 STMICROELECTRONICS [STMicroelectronics], ST10 Datasheet - Page 53

• Manufacturer Part Number: ST10
• Description: 16-BIT MCU WITH 32K BYTE ROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 19 : Demultiplexed bus characteristics (continued)
Notes 1. Guaranteed by design characterization.
t
t
t
t
t
t
t
t
t
53
68
t
t
43
46
47
48
49
50
51
55
57
Symbol
1
1
2. RW-delay and tA refer to the next following bus cycle.
3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
CC
SR
SR
CC
CC
CC
SR
SR
SR
CC
CC
ALE falling edge to RdCS, WrCS
(no RW-delay)
RdCS to Valid Data In (with
RW-delay)
RdCS to Valid Data In (no
RW-delay)
RdCS, WrCS Low Time (with
RW-delay)
RdCS, WrCS Low Time (no
RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS (with
RW-delay)
Data float after RdCS (no RW-delay)
Address hold after RdCS, WrCS
Data hold after WrCS
Parameter
-10 + t
30 + t
50 + t
26 + t
-4 + t
6 + t
Min.
Max. CPU Clock
–
–
0
–
–
F
A
C
C
C
F
= 25MHz
16 + t
36 + t
20 + t
0 + t
Max.
–
–
–
–
–
–
–
F
C
C
F
2TCL - 10 + t
3TCL - 10 + t
2TCL - 14 + t
TCL - 14 + t
-10 + t
-4 + t
1/2TCL = 1 to 25MHz
Min.
Variable CPU Clock
–
–
0
–
–
A
F
F
C
C
C
2TCL - 24 + t
3TCL - 24 + t
2TCL - 20 + t
TCL - 20 + t
Max.
–
–
–
–
–
–
–
ST10C167
F
C
C
F
53/65
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns