ST10 STMICROELECTRONICS [STMicroelectronics], ST10 Datasheet - Page 62

• Manufacturer Part Number: ST10
• Description: 16-BIT MCU WITH 32K BYTE ROM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued)
The formula for SSC Clock Cycle time is : t
Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.
Figure 25 : SSC master timing
Notes 1. The phase and polarity of shift and latch edge of SCLK is programmable.This figure uses the leading clock edge as shift edge (drawn
Slave mode
V
Note
62/65
t
t
CC
t
t
t
t
t
t
t
t
t
317p
318p
310
311
312
313
314
315
316
317
318
Symbol
= 5V 10%, V
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
1. Timing guaranteed by design.
SCLK
MTSR
MRST
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
SR Read data setup time before latch edge,
SR Read data hold time after latch edge,
SR Read data setup time before latch edge,
SR Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
phase error detection on (SSCPEN = 1)
phase error detection off (SSCPEN = 0)
phase error detection off (SSCPEN = 0)
1)
SS
= 0V, CPU clock = 25MHz, T
t
305
Parameter
1st.In Bit
t
307
t
300
1st Out Bit
t
308
t
t
301
305
t
304
300
2nd Out Bit
2nd.In Bit
t
302
= 4 TCL * (<SSCBR> + 1)
Max Baud rate=6.25MBd
A
(<SSCBR> = 0001h)
Min.
160
100
140
t
= -40 to +125 C, C
70
70
10
303
–
–
–
0
0
t
306
2)
Max.
160
10
10
54
–
–
–
–
–
–
–
t
305
L
Last.In Bit
t
= 100pF
307
(<SSCBR>=0001h-FFFFh )
t
t
4TCL + 20
6TCL + 20
310
310
Last Out Bit
8 TCL
Variable Baud rate
Min.
t
10
/2 - 10
/2 - 10
308
–
–
–
0
0
262144 TCL
2 TCL + 14
Max.
10
10
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns