ST10 STMICROELECTRONICS [STMicroelectronics], ST10 Datasheet - Page 58
ST10
Manufacturer Part Number
ST10
Description
16-BIT MCU WITH 32K BYTE ROM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.ST10.pdf
(65 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10-12-12S
Manufacturer:
ARTESYN
Quantity:
12 000
Company:
Part Number:
ST10-12-15S
Manufacturer:
ARCH
Quantity:
12 000
Company:
Part Number:
ST10-12-24S
Manufacturer:
ARCH
Quantity:
12 000
Company:
Part Number:
ST10-12-3.3S
Manufacturer:
ARCH
Quantity:
12 000
Company:
Part Number:
ST10-12-5S
Manufacturer:
MINMAX
Quantity:
12 000
ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued)
XX.4.11 - CLKOUT and READY
V
C
C
Table 20 : CLKOUT and READY characteristics
Notes 1.These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
58/65
DD
t
t
t
t
t
t
t
t
t
t
t
t
L
L
Symbol
29
30
31
32
33
34
35
36
37
58
59
60
(for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF
(for Port 6, CS) = 100pF
= 5V
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time
for deactivating READY.
The 2t
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
A
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CLKOUT rising edge to ALE falling edge
Synchronous READY setup time
to CLKOUT
Synchronous READY hold time
after CLKOUT
Asynchronous READY low time
Asynchronous READY setup time
Asynchronous READY hold time
Async. READY hold time after RD, WR high
(Demultiplexed Bus)
and t
10%, V
C
refer to the next following bus cycle, t
SS
= 0V, T
Parameter
A
2
= -40 to +125 C
1
1
F
refers to the current bus cycle.
0 + t
Min.
Max. CPU Clock
40
14
10
14
54
14
–
–
4
4
0
A
= 25MHz
+ t C + t
10 + t
0 + 2t
Max.
40
–
–
4
4
–
–
–
–
–
A
A
F
2
2TCL + 14
TCL – 10
TCL – 6
0 + t
2TCL
Min.
1/2TCL = 1 to 25MHz
14
14
Variable CPU Clock
–
–
4
4
0
A
+ 2t
TCL - 20
A
10 + t
2TCL
Max.
+ t C + t
–
–
4
4
–
–
–
–
–
A
F
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns