h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 599

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

11. Note on ICDR read and ICCR access in slave transmit mode
12. Note on TRS bit setting in slave mode
In I
to ICCR during the time shaded in figure 17.26.
However, such read and write operations cause no problem in interrupt handling processing
that is generated in synchronization with the rising edge of the 9th clock pulse because the
shaded time has passed before making the transition to interrupt handling.
To handle interrupts securely, be sure to keep either of the following conditions.
In I
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 17.27), the bit value becomes valid immediately
when it is set.
However, if the TRS bit is set during the other time (the time indicated as (b) in figure 17.27),
the bit value is suspended and remains invalid until the rising edge of the 9th clock pulse or the
stop condition is detected.
Therefore, when the address is received after the restart condition is input without the stop
condition, the effective TRS bit value remains 1 (transmit mode) internally and thus the
acknowledge bit is not transmitted after the address has been received at the 9th clock pulse.
2
Read ICDR data that has been received so far or read from or write to ICCR before starting
the receive operation of the next slave address.
Monitor the BC2 to BC0 counter in ICMR; when the count is 000 (8th or 9th clock pulse),
wait for at least two transfer clock times in order to read from ICDR or read from or write
to ICCR during the time other than the shaded time.
2
C bus interface slave transmit mode, do not read from ICDR or do not read from or write
C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
Figure 17.26 ICDR Read and ICCR Access Timing in Slave Transmit Mode
TRS bit
SDA
SCL
Address reception
R/W
8
The rise of the 9th clock is detected
Waveform at problem occurrence
A
9
ICDR read and ICCR read/write are disabled
(Period of 6 system clocks)
Rev. 3.00 Jan 25, 2006 page 547 of 872
Section 17 I
Data transmission
ICDR write
2
C Bus Interface (IIC)
Bit 7
REJ09B0286-0300