MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 14

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

Operation
BANK/ROW ACTIVATION
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated (see Figure 3).
a READ or WRITE command may be issued to that row,
subject to the
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
which covers any case where 2 <
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles).
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
RRD.
Before any READ or WRITE commands can be is-
After opening a row (issuing an ACTIVE command),
A subsequent ACTIVE command to a different row
A subsequent ACTIVE command to another bank
t
RCD specification.
COMMAND
Example: Meeting
CLK
ACTIVE
T0
t
RCD (MIN)/
t
RCD (MIN) should
t
RC.
t
RCD specifi-
t
RCD (MIN) When 2 <
t
CK
NOP
T1
Figure 4
3.
t
RCD
14
A0–A10, A11
BA0, BA1
T2
NOP
Activating a Specific Row in a
RAS#
CAS#
WE#
CKE
CLK
CS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (MIN)/
HIGH
Specific Bank
READ or
WRITE
T3
Figure 3
64Mb: x4, x8, x16
DON’T CARE
t
CK < 3
ADDRESS
ADDRESS
BANK
ROW
T4
©2003, Micron Technology, Inc.
SDRAM