MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 40

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTES: 1. No maximum time limit for Self Refresh mode.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
DQML, DQMH
AH
AS
CH
CL
CK(3)
CK(2)
CKH
COMMAND
A0-A9, A11
BA0, BA1
2.
DQM/
CKE
A10
CLK
t
DQ
XSR requires minimum of two clocks regardless of frequency and timing.
1.5
2.5
2.5
1
6
–
1
High-Z
-6
Precharge all
t CKS
active banks
t CMS
t
SINGLE BANK
AS
PRECHARGE
ALL BANKS
BANK(S)
T0
t CKH
0.8
1.5
2.5
2.5
7.5
0.8
t CMH
t
AH
7
t CK
-7E
1.5
2.5
2.5
7.5
0.8
t RP
10
0.8
T1
NOP
-75
t CH
Enter self refresh mode
10
2
3
3
8
1
1
t CKS
t CL
-8E
SELF REFRESH MODE
REFRESH
CLK stable prior to exiting
AUTO
T2
self refresh mode
ns
ns
ns
ns
ns
ns
ns
t
RAS(MAX) applies to non-Self Refresh mode.
t RAS(MIN)
(
(
(
(
(
(
)
)
(
(
)
(
)
(
(
)
(
)
(
)
)
)
)
)
)
(
)
(
(
(
(
(
)
(
(
)
(
)
(
(
)
(
)
)
(
(
)
)
)
)
)
)
(
(
)
)
)
)
(
(
)
40
(
)
)
1
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
CKS
CMH
CMS
RAS
RP
XSR
(Restart refresh time base)
Exit self refresh mode
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Tn + 1
42
18
70
1.5
1.5
1
-6
120,000
t XSR
NOP
(
(
(
(
(
(
(
(
)
(
)
)
)
)
(
)
)
(
(
(
(
2
)
)
(
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
)
(
)
(
)
(
)
(
)
(
)
)
(
)
)
)
)
)
)
)
1.5
0.8
1.5
)
37 120,000
15
67
or COMMAND
-7E
64Mb: x4, x8, x16
INHIBIT
To + 1
1.5
0.8
1.5
44 120,000
20
75
-75
To + 2
REFRESH
AUTO
©2003, Micron Technology, Inc.
2
1
2
SDRAM
50
20
80
-8E
DON’T CARE
120,000
ns
ns
ns
ns
ns
ns