MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 43

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
DQML, DQMH
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
t
t
AC(3)
AC(2)
AH
AS
CH
CL
CK(3)
CK(2)
CKH
CKS
COMMAND
A0-A9, A11
BA0, BA1
DQM /
CKE
CLK
A10
DQ
2. x16: A8, A9 and A11 = “Don’t Care”
3. PRECHARGE command not allowed else
1.5
2.5
2.5
1.5
t CMS
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CKS
1
6
–
1
t AS
t AS
t AS
ACTIVE
-6
ROW
ROW
BANK
T0
t CMH
5.5
t CKH
t AH
t AH
t AH
–
t RCD
t RAS
t RC
0.8
1.5
2.5
2.5
7.5
0.8
1.5
7
t CK
-7E
T1
5.4
5.4
NOP
SINGLE READ – WITHOUT AUTO PRECHARGE
DISABLE AUTO PRECHARGE
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
t CMS
-75
t CL
COLUMN m
5.4
BANK
T2
READ
6
t CMH
t CH
CAS Latency
2
10
1
2
3
3
8
1
2
-8E
t
RAS would be violated.
6
6
T3
NOP
t LZ
t AC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43
T4
NOP
D
OUT
t OH
3
t HZ
m
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
t
t
CMH
CMS
HZ(3)
HZ(2)
LZ
OH
RAS
RC
RCD
RP
SINGLE BANKS
PRECHARGE
ALL BANKS
BANK(S)
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1.5
42 120,000
60
18
18
1
1
2
t RP
-6
5.5
–
T6
NOP
0.8
1.5
37 120,000
60
15
15
1
3
-7E
64Mb: x4, x8, x16
5.4
5.4
1
ACTIVE
BANK
ROW
T7
ROW
0.8
1.5
44 120,000
66
20
20
1
3
-75
5.4
6
©2003, Micron Technology, Inc.
SDRAM
50 120,000
70
20
20
T8
1
2
1
3
NOP
-8E
DON’T CARE
UNDEFINED
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns