MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 50

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
DQML, DQMH
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
t
AH
AS
CH
CL
CK(3)
CK(2)
CKH
CKS
CMH
COMMAND
A0-A9, A11
BA0, BA1
DQM /
CKE
A10
CLK
DQ
2. 15ns is required between <D
3. x16: A8, A9 and A11 = “Don’t Care”
4. PRECHARGE command not allowed else
1.5
2.5
2.5
1.5
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CMS
t CKS
1
6
–
1
1
t AS
t AS
t AS
-6
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
7
-7E
t CK
T1
NOP
SINGLE WRITE – WITHOUT AUTO PRECHARGE
DISABLE AUTO PRECHARGE
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
-75
t CMS
t CL
t DS
COLUMN m 3
IN
m> and the PRECHARGE command, regardless of frequency.
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t WR
10
1
2
3
3
8
1
2
1
2
-8E
t
RAS would be violated.
NOP 4
T3
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
NOP 4
T4
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1.5
1.5
42 120,000
60
18
18
12
1
-6
T6
NOP
t RP
1.5
0.8
1.5
37 120,000
60
15
15
14
-7E
64Mb: x4, x8, x16
1
BANK
ROW
ACTIVE
1.5
0.8
1.5
44 120,000
66
20
20
15
T7
-75
©2003, Micron Technology, Inc.
SDRAM
50 120,000
70
20
20
15
2
1
2
DON’T CARE
T8
-8E
NOP
ns
ns
ns
ns
ns
ns
ns
ns