MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 37

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
DQML, DQMH
SYMBOL*
t
t
t
t
t
AH
AS
CH
CL
CK(3)
COMMAND
A0-A9, A11
Precharge all
DQM /
BA0, BA1
active banks
CKE
CLK
A10
DQ
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
2.5
2.5
1
6
t CMS
High-Z
-6
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
t CMH
t CKH
t AH
0.8
1.5
2.5
2.5
7
-7E
Two clock cycles
All banks idle, enter
power-down mode
t CK
0.8
1.5
2.5
2.5
7.5
T1
-75
NOP
1
2
3
3
8
t CKS
t CL
-8E
POWER-DOWN MODE
T2
NOP
Input buffers gated off while in
power-down mode
t CH
ns
ns
ns
ns
ns
37
Exit power-down mode
SYMBOL*
t
t
t
t
t
CK(2)
CKH
CKS
CMH
CMS
(
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(
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(
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(
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(
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
1.5
1
–
1
1
-6
7.5
0.8
1.5
0.8
1.5
t CKS
-7E
64Mb: x4, x8, x16
Tn + 1
NOP
All banks idle
0.8
1.5
0.8
1.5
10
-75
Tn + 2
©2003, Micron Technology, Inc.
ACTIVE
10
1
2
1
2
SDRAM
ROW
ROW
BANK
-8E
DON’T CARE
ns
ns
ns
ns
ns