MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 21

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

WRITEs
as shown in Figure 13.
provided with the WRITE command, and auto
precharge is either enabled or disabled for that access.
If auto precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
ment will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to column 0 and
continue.)
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
WRITE bursts are initiated with a WRITE command,
The starting column and bank addresses are
During WRITE bursts, the first valid data-in ele-
Data for any WRITE burst may be truncated with a
A8, A9, A11: x16
A9, A11: x8
A0-A9: x4
A0-A8: x8
A0-A7: x16
A11: x4
BA0,1
CAS#
RAS#
WE#
A10
CKE
CLK
CS#
WRITE Command
HIGH
Figure 13
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
COLUMN
ADDRESS
ADDRESS
BANK
21
An example is shown in Figure 15. Data n + 1 is either
the last of a burst of two or the last desired of a longer
burst. The 64Mb SDRAM uses a pipelined architecture
and therefore does not require the 2n rule associated
with a prefetch architecture. A WRITE command can
be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses
within a page can be performed to the same bank, as
shown in Figure 16, or each subsequent WRITE may be
performed to a different bank.
COMMAND
ADDRESS
CLK
DQ
COMMAND
NOTE: DQM is LOW. Each WRITE command may
ADDRESS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOTE: Burst length = 2. DQM is LOW.
TRANSITIONING DATA
CLK
WRITE
BANK,
be to any bank.
COL n
DQ
TRANSITIONING DATA
T0
D
n
IN
WRITE to WRITE
WRITE Burst
WRITE
BANK,
Figure 14
Figure 15
COL n
D
T0
n
IN
NOP
n + 1
T1
D
IN
64Mb: x4, x8, x16
n + 1
NOP
T1
D
NOP
T2
IN
DON’T CARE
DON’T CARE
WRITE
BANK,
COL b
T3
NOP
T2
D
©2003, Micron Technology, Inc.
b
IN
SDRAM