MT48LC16M4A2 Micron Technology, MT48LC16M4A2 Datasheet - Page 36

• Manufacturer Part Number: MT48LC16M4A2
• Description: SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

DQML, DQMH
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. If CS# is HIGH at clock HIGH time, all commands applied are NOP.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
SYMBOL*
t
t
t
t
t
t
t
AH
AS
CH
CL
CK(3)
CK(2)
CKH
COMMAND
A0-A9, A11
DQM /
BA0, BA1
CLK
CKE
A10
DQ
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
2.5
2.5
T = 100µs
(
1
6
–
1
(
(
(
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Power-up:
V
CLK stable
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(
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)
MIN
DD
-6
and
t CKS
t CMS
T0
NOP
t CKH
High-Z
t CMH
0.8
1.5
2.5
2.5
7.5
0.8
7
-7E
SINGLE BANK
ALL BANKS
t CK
t CMS
BANKS
PRECHARGE
ALL
T1
INITIALIZE AND LOAD MODE REGISTER
0.8
1.5
2.5
2.5
7.5
0.8
10
t CMH
t RP
Precharge
all banks
-75
(
(
(
(
(
(
(
(
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(
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(
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(
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(
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(
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(
(
(
(
(
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)
t CMS
Tn + 1
REFRESH
10
AUTO
1
2
3
3
8
1
-8E
t CMH
t CH
AUTO REFRESH
t RFC
NOP
ns
ns
ns
ns
ns
ns
ns
(
(
(
(
(
(
(
(
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(
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(
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(
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)
)
NOP
36
t CL
To + 1
REFRESH
SYMBOL*
t
t
t
t
t
t
AUTO
CKS
CMH
CMS
MRD
RFC
RP
AUTO REFRESH
3
t RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
1.5
60
18
1
2
(
(
(
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(
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(
(
(
(
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(
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(
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)
-6
NOP
t AS
t AS
1.5
0.8
1.5
66
15
LOAD MODE
2
Tp + 1
REGISTER
-7E
CODE
CODE
1
64Mb: x4, x8, x16
t AH
t AH
Program Mode Register
1.5
0.8
1.5
66
20
2
t MRD
-75
Tp + 2
NOP
©2003, Micron Technology, Inc.
70
20
2
1
2
2
SDRAM
-8E
2, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE
t
ns
ns
ns
ns
ns
CK