TDA935x Philips, TDA935x Datasheet - Page 11

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
FUNCTIONAL DESCRIPTION OF THE 80C51
The functionality of the micro-controller used on this
device is described here with reference to the industry
standard 80C51 micro-controller. A full description of its
functionality can be found in the 80C51 based 8-bit
micro-controllers - Philips Semiconductors (ref. IC20).
Features of the 80c51
Memory Organisation
The device has the capability of a maximum of 128K Bytes
of PROGRAM ROM and 12K Bytes of DATA RAM. The
OSD (& Closed Caption) only version has a 2K RAM and
a maximum of 64K ROM, the 1 page teletext version has
a 3K RAM and also a maximum of 64K ROM whilst the 10
page teletext version has a 12K RAM and a maximum of
128K ROM.
ROM Organisation
The 64K device has a continuous address space from 0 to
64K. The 128K is arranged in four banks of 32K. One of
2001 Jan 18
80C51 micro-controller core standard instruction set and
timing.
1 s machine cycle.
Maximum 128K x 8-bit Program ROM.
Maximum of 12K x 8-bit Auxiliary RAM.
8-Level Interrupt Controller for individual enable/disable
with two level priority.
Two 16-bit Timer/Counters.
Additional 16-bit Timer with 8-bit Pre-scaler.
WatchDog Timer.
Auxiliary RAM Page Pointer.
16-bit Data pointer
Idle, Stand-by and Power-Down modes.
13 General I/O.
Four 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analogue signals.
One 14-bit PWM for Voltage Synthesis tuner control.
8-bit ADC with 4 multiplexed inputs.
2 high current outputs for directly driving LED’s etc.
I
TV signal processor-Teletext decoder with
embedded -Controller
2
C Byte Level bus interface.
2K (OSD only version) Auxiliary RAM, maximum
of 1.25K required for Display
3K (1 page teletext version) Auxiliary RAM,
maximum of 2K required for Display
12K (10 page teletext version) Auxiliary RAM,
maximum of 10K required for Display
11
the 32K banks is common and is always addressable. The
other three banks (Bank0, Bank1, Bank2) can be
accessed by selecting the right bank via the SFR ROMBK
bits 1/0.
RAM Organisation
The Internal Data RAM is organised into two areas, Data
Memory and Special Function Registers (SFRs) as shown
in Fig.5.
D
The Data memory is 256 x 8-bits and occupies the address
range 00 to FF Hex when using Indirect addressing and 00
to 7F Hex when using direct addressing. The SFRs occupy
the address range 80 Hex to FF Hex and are accessible
using Direct addressing only. The lower 128 Bytes of Data
memory are mapped as shown in Fig.6. The lowest 32
ATA
Lower
Upper
128
128
M
8000H
FFFFH
EMORY
Bank0
32K
FFH
7FH
80H
00H
TDA935X/6X/8X PS/N2 series
Fig.4 ROM Bank Switching memory map
Data Memory
Addressing
and Indirect
by Indirect
Fig.5 Internal Data Memory
Accessible
Addressing
Accessible
by Direct
only
8000H
0000H
FFFFH
7FFFH
Common
Bank1
32K
32K
Tentative Device Specification
Special Function Registers
Addressing
Accessible
by Direct
8000H
FFFFH
only
Bank2
32K