TDA935x Philips, TDA935x Datasheet - Page 32

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
different priority level are received simultaneously, the
request with the highest priority level is serviced. If
requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence as defined in Table 4.
I
The processor acknowledges an interrupt request by
executing a hardware generated LCALL to the appropriate
servicing routine. The interrupt vector addresses are
shown in Table 4.
L
The external interrupt can be programmed to be either
level-activated or transition activated by setting or clearing
the IT0/1 bits in the Timer Control SFR(TCON).
The external interrupt INT1 differs from the standard
80C51 in that it is activated on both edges when in edge
sensitive mode. This is to allow software pulse width
measurement for handling remote control inputs.
Timer/Counter
Two 16 bit timers/counters are incorporated Timer0 and
Timer1. Both can be configured to operate as either timers
or event counters.
In Timer mode, the register is incremented on every
machine cycle. It is therefore counting machine cycles.
Since the machine cycle consists of 12 oscillator periods,
the count rate is 1/12 Fosc = 1MHz.
2001 Jan 18
NTERRUPT
EVEL
Table 5 External Interrupt Activation
TV signal processor-Teletext decoder with
embedded -Controller
ITx
0
1
/E
Table 4 Interrupt Priority (within same level)
DGE
Active low
V
EBUSY
Source
ET2PR
ECTOR
I
Level
NTERRUPT
ECC
EX0
ET0
EX1
ET1
ES2
A
DDRESS
INT0 = Negative Edge
INT1 = Positive and Negative Edge
Priority within level
Highest
Lowest
Edge
Interrupt Vector
000BH
001BH
002BH
003BH
0003H
0013H
0023H
0033H
32
In Counter mode, the register is incremented in response
to a negative transition at its corresponding external pin
T0/1. Since the pins T0/1 are sampled once per machine
cycle it takes two machine cycles to recognise a transition,
this gives a maximum count rate of 1/24 Fosc = 0.5MHz.
There are six special function registers used to control the
timers/counters as defined in Table 6.
TF1 TR TF0 TR IE1 IT1 IE0 IT0
Fig.10 Timer/Counter Control (TCON) register
Symbol
Symbol
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
TDA935X/6X/8X PS/N2 series
Table 6 Timer/Counter Registers
Position
TCON.7
TCON.6
TCON.5
TCON.4
Position
TCON.3
TCON.2
TCON.1
TCON.0
TMOD
TCON
SFR
TH0
TH1
TL0
TL1
Name and Significance
Timer 1 overflow flag. Set by hard-
ware on timer/counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Timer 1 Run control bit. Set/cleared
by software to turn timer.counter
on/off.
Timer 0 overflow flag. Set by hard-
ware on timer/counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Timer 0 Run control bit. Set/cleared
by software to turn timer.counter
on/off.
Name and Significance
Interrupt 1 Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.
Interrupt 1 Type control bit.
Set/cleared by software to specify fall-
ing edge/low level triggered external
interrupts.
Interrupt 0 Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.
Interrupt 0 Type control bit.
Set/cleared by software to specify fall-
ing edge/low level triggered external
interrupts.
Tentative Device Specification
Address
8AH
8BH
8CH
8DH
88H
89H