TDA935x Philips, TDA935x Datasheet - Page 30

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
To enter Stand-by mode, the STAND-BY bit in the
ROMBANK register must be set. Once in Stand-By, the
XTAL oscillator continues to run, but the internal clock to
Acquisition and Display are gated out. However, the clocks
to the 80c51 CPU Core, Memory Interface, I2C,
Timer/Counters, WatchDog Timer and Pulse Width
Modulators are maintained. Since the output values on
RGB and VDS are maintained the display output must be
disabled before entering this mode.
This mode may be used in conjunction with both Idle and
Power-Down modes. Hence, prior to entering either Idle or
Power-Down, the STAND-BY bit may be set, thus allowing
wake-up of the 80c51 CPU core without fully waking the
entire device (This enables detection of a Remote Control
source in a power saving mode).
I
During Idle mode, Acquisition, Display and the CPU
sections of the device are disabled. The following
functions remain active:-
To enter Idle mode the IDL bit in the PCON register must
be set. The WatchDog timer must be disabled prior to
entering Idle to prevent the device being reset. Once in Idle
mode, the XTAL oscillator continues to run, but the internal
clock to the CPU, Acquisition and Display are gated out.
However, the clocks to the Memory Interface, I2C,
Timer/Counters, WatchDog Timer and Pulse Width
Modulators are maintained. The CPU state is frozen along
with the status of all SFRs, internal RAM contents are
maintained, as are the device output pin values. Since the
output values on RGB and VDS are maintained the
Display output must be disabled before entering this
mode.
There are three methods available to recover from Idle:-
2001 Jan 18
DLE
Memory Interface
I2C
Timer/Counters
WatchDog Timer
SAD & PWMs
Assertion of an enabled interrupt will cause the IDL bit to
be cleared by hardware, thus terminating Idle mode.
The interrupt is serviced, and following the instruction
RETI, the next instruction to be executed will be the one
after the instruction that put the device into Idle mode.
A second method of exiting Idle is via an Interrupt
generated by the SAD DC Compare circuit. When
Painter is configured in this mode, detection of an
analogue threshold at the input to the SAD may be used
to trigger wake-up of the device i.e. TV Front Panel
Key-press. As above, the interrupt is serviced, and
following the instruction RETI, the next instruction to be
TV signal processor-Teletext decoder with
embedded -Controller
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30
P
In Power Down mode the XTAL oscillator still runs, and
differential clock transmitter is active. The contents of all
SFRs and Data memory are maintained, however, the
contents of the Auxiliary/Display memory are lost. The port
pins maintain the values defined by their associated SFRs.
Since the output values on RGB and VDS are maintained
the Display output must be made inactive before entering
Power Down mode.
The power down mode is activated by setting the PD bit in
the PCON register. It is advised to disable the WatchDog
timer prior to entering Power down. Recovery from
Power-Down takes several milli-seconds as the oscillator
must be given time to stabilise.
There are three methods of exiting power down:-
OWER
executed will be the one following the instruction that put
the device into Idle.
The third method of terminating Idle mode is with an
external hardware reset. Since the oscillator is running,
the hardware reset need only be active for two machine
cycles (24 clocks at 12MHz) to complete the reset
operation. Reset defines all SFRs and Display memory
to a pre-defined state, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ’0000’.
An External interrupt provides the first mechanism for
waking from Power-Down. Since the clock is stopped,
external interrupts needs to be set level sensitive prior to
entering Power-Down. The interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one after the instruction that put the
device into Power-Down mode.
A second method of exiting Power-Down is via an
Interrupt generated by the SAD DC Compare circuit.
When Painter is configured in this mode, detection of a
certain analogue threshold at the input to the SAD may
be used to trigger wake-up of the device i.e. TV Front
Panel Key-press. As above, the interrupt is serviced,
and following the instruction RETI, the next instruction to
be executed will be the one following the instruction that
put the device into Power-Down.
The third method of terminating the Power-Down mode
is with an external hardware reset. Reset defines all
SFRs and Display memory, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ’0000’.
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TDA935X/6X/8X PS/N2 series
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Tentative Device Specification