TDA935x Philips, TDA935x Datasheet - Page 19

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
Table 3 SFR Bit description
2001 Jan 18
S1DAT
S1STA
SAD
SADB
SP
TCON
TV signal processor-Teletext decoder with
embedded -Controller
STAT<4:0>
DC_COMP
Names
SAD<7:4>
SAD<3:0>
DAT<7:0>
CH<1:0>
SP<7>
STO
STA
VHI
TF1
AA
ST
SI
START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus
becomes free. If the device operates in master mode it will generate a repeated START condition.
STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also
be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases
the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware.
Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:
-A START condition is generated in master mode.
-The own slave address has been received during AA=1.
-The general call address has been received while S1ADR.GC and AA=1.
-A data byte has been received or transmitted in master mode (even if arbitration is lost).
-A data byte has been received or transmitted as selected slave.
A STOP or START condition is received as selected slave receiver or transmitter
While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.
Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions
-Own slave address is received.
-General call address is received(S1ADR.GC=1).
-A data byte is received, while the device is programmed to be a master receiver.
-A data byte is received, while the device is selected slave receiver.
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.
I
I
0 - Analogue input voltage less than or equal to DAC voltage.
1 - Analogue input voltage greater then DAC voltage.
ADC Input channel select.
CH<1:0> = 00,ADC3.
CH<1:0> = 01,ADC0.
CH<1:0> = 10,ADC1.
CH<1:0> = 11,ADC2.
Initiate voltage comparison between ADC input Channel and SADB<3:0> value.
Note: Set by Software and reset by Hardware.
Most Significant nibble of DAC input word
0 - Disable DC Comparator mode.
1 - Enable DC Comparator mode.
4-bit SAD value.
Stack Pointer.
88H
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine.
ADD
DAH
D9H
E8H
98H
81H
2
2
C Data.
C Interface Status.
TF1
STAT<4>
DAT<7>
SP<7>
BIT7
VHI
0
TR1
STAT<3>
DAT<6>
CH<1>
SP<6>
BIT6
0
TF0
STAT<2>
DAT<5>
CH<0>
SP<5>
BIT5
0
TR0
DC_COMP
STAT<1>
DAT<4>
SP<4>
BIT4
19
ST
IE1
STAT<0>
SAD<7>
SAD<3>
DAT<3>
SP<3>
BIT3
TDA935X/6X/8X PS/N2 series
IT1
SAD<6>
SAD<2>
DAT<2>
SP<2>
BIT2
0
Tentative Device Specification
IE0
SAD<5>
DAT<1>
SAD<1>
SP<1>
BIT1
0
IT0
SAD<4>
SAD<0>
DAT<0>
SP<0>
BIT0
0
RESET
F8H
00H
00H
00H
07H
00H