TDA935x Philips, TDA935x Datasheet - Page 34

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
SFR and also writing a ‘1’ to the Port bit that the function
occupies.
PWM P
The device has four 6-bit Pulse Width Modulated (PWM)
outputs for analogue control of e.g. volume, balance, bass
and treble. The PWM outputs generate pulse patterns with
a repetition rate of 21.33us, with the high time equal to the
PWM SFR value multiplied by 0.33us. The analogue value
is determined by the ratio of the high time to the repetition
time, a D.C. voltage proportional to the PWM setting is
obtained by means of an external integration network (low
pass filter).
PWM Control
The relevant PWM is enabled by setting the PWM enable
bit PWxE in the PWMx Control register. The high time is
defined by the value PWxV<5:0>
TPWM T
The device has a single 14-bit PWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similar to the normal PWM except the repetition period is
42.66us.
TPWM Control
Two SFRs are used to control the TPWM, they are TDACL
and TDACH. The TPWM is enabled by setting the TPWE
bit in the TDACH SFR. The most significant bits TD<13:7>
alter the high period between 0 and 42.33us. The 7 least
significant bits TD<6:0> extend certain pulses by a further
0.33us. e.g. if TD<6:0> = 01H then 1 in 128 periods will be
extended by 0.33us, if TD<6:0>=02H then 2 in 128 periods
will be extended.
The TPWM will not start to output a new value until TDACH
has been written to. Therefore, if the value is to be
changed, TACL should be written before TDACH.
SAD S
Four successive approximation Analogue to Digital
Converters can be implemented in software by making use
of the on board 8-bit Digital to Analogue Converter and
Analogue Comparator.
SAD Control
The control of the required analogue input is done using
the channel select bits CH<1:0> in the SAD SFR, this
selects the required analogue input to be passed to one of
the inputs of the comparator. The second comparator input
is generated by the DAC whose value is set by the bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare bit
ST in the SAD SFR is set, this must be at least one
2001 Jan 18
TV signal processor-Teletext decoder with
embedded -Controller
OFTWARE
ULSE
UNING
W
IDTH
P
A/D
ULSE
M
ODULATORS
W
IDTH
M
ODULATOR
34
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after the setting of ST.
SAD Input Voltage
The external analogue voltage that is used for comparison
with the internally generated DAC voltage, does not have
the same voltage range due to the 5 V tolerance of the pin.
It is limited to V
For further details refer to the SAA55XX and SAA56XX
Software Analogue to Digital Converter Application Note:
SPG/AN99022.
SAD DC Comparator Mode
The SAD module incorporates a DC Comparator mode
which is selected using the ’DC_COMP’ control bit in the
SADB SFR. This mode enables the micro-controller to
detect a threshold crossing at the input to the selected
analogue input pin (P3.0, P3.1, P3.2 or P3.3) of the
Software A/D Converter. A level sensitive interrupt is
generated when the analogue input voltage level at the pin
falls below the analogue output level of the SAD D/A
converter.
This mode is intended to provide the device with a
wake-up mechanism from Power-Down or Idle when a
key-press on the front panel of the TV is detected.
The following software sequence should be used when
utilizing this mode for Power-Down or Idle:-
1. Disable INT1 using the IE SFR.
2. Set INT1 to level sensitive using the TCON SFR.
3. Set the D/A Converter digital input level to the desired
4. Enter DC Compare mode by setting the ’DC_COMP’
ADC0
ADC1
ADC2
ADC3
threshold level using the SAD/SADB SFRs and select
the required input pin (P3.0, P3.1, P3.2 or P3,3) using
CH1, CH0 in the SAD SFR.
enable bit in the SADB SFR.
SAD<7:0>
CH<1:0>
TDA935X/6X/8X PS/N2 series
V
DDP
DDP
Fig.12 SAD Block Diagram
-V
tn
MUX
8-bit
DAC
4-1
where V
Tentative Device Specification
tn
is a maximum of 0.75 V.
+
-
VHI