TDA935x Philips, TDA935x Datasheet - Page 94

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
Notes
1. When the 3.3 V supply is present and the -Controller is active a ‘low-power start-up’ mode can be activated. When
2. On set AGC.
3. This parameter is not tested during production and is just given as application information for the designer of the
4. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
5. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
7. Measured at 10 mV (RMS) top sync input signal.
8. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
9. So called projected zero point, i.e. with switched demodulator.
10. Measured in accordance with the test line given in Fig.36. For the differential phase test the peak white setting is
11. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.37.
12. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal)
13. The test set-up and input conditions are given in Fig.38. The figures are measured with an input signal of
2001 Jan 18
C.7.5
C.7.6
C.7.7
C.7.8
F
C.8.1
C.8.2
IXED BEAM CURRENT SWITCH
TV signal processor-Teletext decoder with
embedded -Controller
NUMBER
all sub-address bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 24H). In this condition the horizontal drive signal has the nominal T
the T
(e.g. closing of the second loop) is continued.
television receiver.
FPLL input signal level).
digital control circuit which uses the clock frequency of the -Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 27H. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
batches which are made in the pilot production period.
The selection between both signals is realised by means of the SVO bit in subaddress 22H.
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
10 mV RMS. This test can only be carried out in a test set-up in which the test options of the IC can be activated.
This because the IF-AGC control input is not available in this IC.
ON
grows gradually from zero to the nominal value. As soon as the 8 V supply is present the switch-on procedure
internal bias voltage
detection level vertical guard
minimum input current to
activate the guard circuit
maximum allowable current
discharge current during
switch-off
discharge time of picture tube
PARAMETER
-
OFF
;
NOTE
59
IVG bit = “1”; note 58
IVG bit = “1”; note 58
CONDITIONS
94
TDA935X/6X/8X PS/N2 series
0.85
MIN.
Tentative Device Specification
3.3
3.45
100
1
1.0
38
TYP.
1.15
MAX.
V
V
mA
ms
mA
OFF
A
UNIT
and