TDA935x Philips, TDA935x Datasheet - Page 13

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
Table 2 SFR Map
2001 Jan 18
ADD
92H
93H
94H
96H
97H
98H
9CH
9DH
9EH
9FH
A0H
A6H
A7H
A8H
B0H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BEH
BFH
C0H
TV signal processor-Teletext decoder with
embedded -Controller
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
TP2H
TP2PR
TP2CRL
P0CFGA
P0CFGB
SADB
TP2CL
TP2CH
P1CFGA
P1CFGB
P2
P2CFGA
P2CFGB
IE
P3
TXT18
TXT19
TXT20
TXT21
TXT22
CCLIN
IP
TXT17
WSS1
WSS2
WSS3
P3CFGA
P3CFGB
TXT0
Names
P1CFGB<7>
TP2CH<7>
TP2H<15>
TP2PR<7>
TP2CL<7>
WSS<13:11>
X24 POSN
P1CFGA<7>
ENABLE
LINE<1>
GPF1<7>
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NOT<3>
Reserved
Reserved
ERROR
DRCS
BIT7
DISP
TEN
EA
0
0
0
0
0
-
-
P0CFGB<6>
P1CFGB<6>
P2CFGB<6>
TP2CH<6>
TP2H<14>
TP2PR<6>
TP2CL<6>
P0CFGA<6>
P1CFGA<6>
P2CFGA<6>
LINES<0>
WSS<13>
DISPLAY
GPF1<6>
PLANES
Reserved
NOT<2>
ACQ<1>
Reserved
Reserved
EBUSY
PBUSY
FORCE
TC<2>
BIT6
DISP
OSD
X24
0
0
0
-
-
-
P0CFGB<5>
P2CFGB<5>
TP2CH<5>
TP2H<13>
TP2PR<5>
TP2CL<5>
P0CFGA<5>
P2CFGA<5>
WSS<12>
GPF1<5>
Reserved
Reserved
Reserved
NOT<1>
SIZE<1>
ACQ<0>
Reserved
Reserved
FRAME
FORCE
TC<1>
CHAR
AUTO
BIT5
PES2
ES2
0
0
0
0
-
-
-
13
P2CFGB<4>
DC_COMP
TP2CH<4>
TP2H<12>
TP2PR<4>
TP2CL<4>
P2CFGA<4>
WSS<3:0>
WSS<7:4>
DISABLE
WSS<11>
HEADER
GPF1<4>
DISP<1>
Reserved
Reserved
Reserved
Reserved
Reserved
NOT<0>
SIZE<0>
Reserved
Reserved
ERROR
ERROR
FORCE
TC<0>
CS<4>
CHAR
ROLL
BIT4
ECC
PCC
0
-
-
TDA935X/6X/8X PS/N2 series
P1CFGB<3>
P2CFGB<3>
P3CFGB<3>
ROW ONLY
OSD LANG
WSS<10:8>
TP2CH<3>
TP2H<11>
TP2PR<3>
TP2CL<3>
P1CFGA<3>
P2CFGA<3>
P3CFGA<3>
DISPLAY
ENABLE
GPF1<3>
DISP<0>
Reserved
Reserved
SAD<3>
Reserved
WSS<3>
WSS<7>
STATUS
ERROR
FORCE
CS<3>
P3<3>
BIT3
ET1
PT1
0
0
-
-
P1CFGB<2>
P2CFGB<2>
P3CFGB<2>
TP2CH<2>
TP2H<10>
TP2PR<2>
TP2CL<2>
P1CFGA<2>
P2CFGA<2>
P3CFGA<2>
DISABLE
WSS<10>
GPF1<2>
SCREEN
Reserved
Reserved
SAD<2>
LAN<2>
COL<2>
WSS<2>
WSS<6>
FRAME
CC ON
CS<2>
P3<2>
BIT2
OSD
EX1
PX1
Tentative Device Specification
0
0
-
-
P1CFGB<1>
P2CFGB<1>
P3CFGB<1>
TP2CRL<1>
TP2CH<1>
I2C PORT0
TP2PR<1>
TP2CL<1>
P1CFGA<1>
P2CFGA<1>
P3CFGA<1>
TP2H<9>
GPF1<1>
SCREEN
Reserved
Reserved
SAD<1>
LAN<1>
COL<1>
WSS<1>
WSS<5>
WSS<9>
VPS ON
BS<1>
CS<1>
P3<1>
TS<1>
BIT1
OSD
ET0
PT0
-
P1CFGB<0>
P2CFGB<0>
P3CFGB<0>
TP2CRL<0>
TP2CH<0>
TP2PR<0>
TP2CL<0>
P1CFGA<0>
P2CFGA<0>
P3CFGA<0>
TP2H<8>
GPF1<0>
SCREEN
Reserved
Reserved
SAD<0>
LAN<0>
COL<0>
WSS<0>
WSS<4>
WSS<8>
CC/TXT
INV ON
BS<0>
CS<0>
P3<0>
TS<0>
P2<0>
BIT0
OSD
EX0
PX0