TDA935x Philips, TDA935x Datasheet - Page 31

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
I/O Facility
I/O
The IC has 13 I/O lines, each is individually addressable,
or form part of 4 parallel addressable ports which are
port0, port1, port2 and port3.
P
All individual ports can be programmed to function in one
of four modes, the mode is defined by two Port
Configuration SFRs. The modes available are Open Drain,
Quasi-bidirectional, High Impedance and Push-Pull.
Open Drain
The Open drain mode can be used for bi-directional
operation of a port. It requires an external pull-up resistor,
the pull-up voltage has a maximum value of 5.5V, to allow
connection of the device into a 5V environment.
Quasi bi-directional
The quasi-bidirectional mode is a combination of open
drain and push pull. It requires an external pull-up resistor
to VDDp (nominally 3.3V). When a signal transition from
0->1 is output from the device, the pad is put into push-pull
mode for one clock cycle (166ns) after which the pad goes
into open drain mode. This mode is used to speed up the
edges of signal transitions. This is the default mode of
operation of the pads after reset.
High Impedance
The high impedance mode can be used for Input only
operation of the port. When using this configuration the two
output transistors are turned off.
Push-Pull
The push pull mode can be used for output only. In this
mode the signal is driven to either 0V or VDDp, which is
nominally 3.3V.
Interrupt System
The device has 8 interrupt sources, each of which can be
enabled or disabled. When enabled, each interrupt can be
assigned one of two priority levels. There are four
interrupts that are common to the 80C51, two of these are
external interrupts (EX0 and EX1) and the other two are
timer interrupts (ET0 and ET1). There is also one interrupt
(ES2) connected to the 80c51 micro-controller IIC
peripheral for Transmit and Receive operation.
The TDA935X/6x/8x family of devices have an additional
16-bit Timer (with 8-bit Pre-scaler). To accommodate this,
another interrupt ET2PR has been added to indicate timer
overflow.
2001 Jan 18
ORT TYPE
TV signal processor-Teletext decoder with
embedded -Controller
PORTS
31
In addition to the conventional 80c51, two application
specific interrupts are incorporated internal to the device
which have the following functionality:-
CC (Closed Caption Data Ready Interrupt) - This
interrupt is generated when the device is configured for
Closed Caption acquisition. The interrupt is activated at
the end of the currently selected Slice Line as defined in
the CCLIN SFR.
BUSY (Display Busy Interrupt) - An interrupt is
generated when the Display enters either a Horizontal or
Vertical Blanking Period. i.e. Indicates when the
micro-controller can update the Display RAM without
causing undesired effects on the screen. This interrupt can
be configured in one of two modes using the MMR
Configuration Register (Address 87FF, Bit-3 [TXT/V]):-
I
Each of the individual interrupts can be enabled or
disabled by setting or clearing the relevant bit in the
interrupt enable SFRs (IE and IEN1). All interrupt sources
can also be globally disabled by clearing the EA bit (IE.7).
I
Each interrupt source can be assigned one of two priority
levels. The interrupt priorities are defined by the interrupt
priority SFRs (IP and IP1). A low priority interrupt can be
interrupted by a high priority interrupt, but not by another
low priority interrupt. A high priority interrupt can not be
interrupted by any other interrupt source. If two requests of
NTERRUPT
NTERRUPT
TeXT Display Busy: An interrupt is generated on each
active horizontal display line when the Horizontal
Blanking Period is entered.
Vertical Display Busy: An interrupt is generated on each
vertical display field when the Vertical Blanking Period is
entered.
EBUSY
ET2PR
Interrupt
Source
EX0
ET0
EX1
ET1
ECC
ES2
TDA935X/6X/8X PS/N2 series
E
E
NABLE
NABLE
Source
Enable
IE.0:6
IE1.0
Fig.9 Interrupt Structure
S
P
TRUCTURE
RIORITY
Global
Enable
IE.7
Tentative Device Specification
Priority
Control
IP.0:6
IP1.0
H1
L1
H2
L2
H3
L3
H4
L4
H5
L5
H6
L6
H7
L7
H8
L8
Highest Priority Level1
Highest Priority Level0
Lowest Priority Level1
Lowest Priority Level0