TDA935x Philips, TDA935x Datasheet - Page 12
![no-image](/images/no-image-200.jpg)
TDA935x
Manufacturer Part Number
TDA935x
Description
TV Signal Processor-Teletext Decoder with Embedded u-Controller
Manufacturer
Philips
Datasheet
1.TDA935X.pdf
(118 pages)
- Current page: 12 of 118
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Philips Semiconductors
bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable
memory space. The upper 128 bytes are not allocated for any special area or functions.
SFR M
The Special Function Register (SFR) space is used for port latches, counters/timers, peripheral control, data capture and
display. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both
bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR
map in address order is shown in Table 2.
Table 2 SFR Map
2001 Jan 18
ADD
80H
81H
82H
83H
84H
85H
87H
88H
89H
8AH
8BH
8CH
8DH
90H
91H
TV signal processor-Teletext decoder with
embedded -Controller
EMORY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0
SP
DPL
DPH
IEN1
IP1
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
P1
TP2L
Names
TP2L<7>
Reserved
DPH<7>
DPL<7>
TH0<7>
TH1<7>
TL0<7>
TL1<7>
SP<7>
P1<7>
GATE
BIT7
TF1
0
-
-
TP2L<6>
DPH<6>
DPL<6>
TH0<6>
TH1<6>
TL0<6>
TL1<6>
P0<6>
SP<6>
P1<6>
BIT6
ARD
TR1
C/T
-
-
Fig.6
11 = BANK3
10 = BANK2
01 = BANK1
00 = BANK0
Bank Select
Bits in PSW
Lower 128 Bytes of Internal RAM
TP2L<5>
DPH<5>
Reserved
DPL<5>
TH0<5>
TH1<5>
TL0<5>
TL1<5>
P0<5>
SP<5>
BIT5
TF0
RFI
M1
-
-
7FH
2FH
1FH
0FH
20H
18H
17H
10H
08H
07H
00H
12
TP2L<4>
Reserved
DPH<4>
Reserved
DPL<4>
TH0<4>
TH1<4>
TL0<4>
TL1<4>
SP<4>
BIT4
WLE
TR0
M0
-
-
TDA935X/6X/8X PS/N2 series
TP2L<3>
Reserved
DPH<3>
DPL<3>
TH0<3>
TH1<3>
TL0<3>
TL1<3>
SP<3>
P1<3>
GATE
BIT3
GF1
IE1
-
-
TP2L<2>
Reserved
DPH<2>
DPL<2>
TH0<2>
TH1<2>
TL0<2>
TL1<2>
SP<2>
P1<2>
BIT2
GF0
C/T
IT1
Tentative Device Specification
-
-
TP2L<1>
Reserved
DPH<1>
DPL<1>
TH0<1>
TH1<1>
TL0<1>
TL1<1>
SP<1>
P1<1>
BIT1
IE0
M1
PD
-
-
TP2L<0>
Reserved
DPH<0>
DPL<0>
TH0<0>
TH1<0>
TL0<0>
TL1<0>
SP<0>
P1<0>
BIT0
ET2
PT2
IDL
IT0
M0
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