TDA935x Philips, TDA935x Datasheet - Page 21

• Manufacturer Part Number: TDA935x
• Description: TV Signal Processor-Teletext Decoder with Embedded u-Controller
• Manufacturer: Philips

Philips Semiconductors
Table 3 SFR Bit description
2001 Jan 18
TP2CL
TP2CH
TP2H
TP2L
TP2PR
TP2CRL
TEST
TXT0
TV signal processor-Teletext decoder with
embedded -Controller
TP2CH<7:0>
TP2CL<7:0>
TP2CRL<0>
TP2CRL<1>
TP2H<7:0>
TP2H<7:0>
TEST<2:0>
TEST<4:3>
TEST<7:5>
TP2L<7:0>
X24 POSN
Names
M1,M0
Mode Control bits Timer/Counter 0.
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler.
M1,M0 = 01, 16 bit time interval or event counter.
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0.
M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter.
Indicate the low byte of the Time 2 current value.
Indicate the high byte of the Time 2 current value.
Timer 2 high byte, never change unless updated by the software.
Timer 2 low byte, never change unless updated by the software.
Timer 2 Pre-scaler, never change unless updated by the software.
Timer 2 Control.
0 - Timer 2 disabled.
1 - Timer 2 enabled.
Timer 2 Status.
0 - No Overflow.
1 - Overflow.
Program Type bit SEL<2:0>.
011 - Display Dram test.
001 - Acquisition1 test.
010 - Acquisition2 test
Functional test mode bits, set via mode select logic.
Dram Size.
000 - 1.5K x 16.
001 - 2K x 16.
010 - 6K x 16.
011 - 7K x 16.
100 - 12K x 16.
101 - 14K x 16.
110 - 1K x 16.
111 - 11K x 16.
0 - Store X/24 in extension memory
1 - Store X/24 in basic page memory with packets 0 to 23
ADD
FDH
9CH
9DH
C0H
92H
91H
93H
94H
TP2CH<7>
TP2CL<7>
TP2PR<7>
X24 POSN
TP2H<7>
TEST<7>
TP2L<7>
BIT7
-
TP2CH<6>
TP2CL<6>
TP2PR<6>
DISPLAY
TP2H<6>
TEST<6>
TP2L<6>
BIT6
X24
-
TP2CH<5>
TP2CL<5>
TP2PR<5>
TP2H<5>
TEST<5>
TP2L<5>
FRAME
AUTO
BIT5
-
TP2CL<4>
TP2CH<4>
TP2PR<4>
DISABLE
TP2H<4>
TEST<4>
HEADER
TP2L<4>
ROLL
BIT4
21
-
TP2CH<3>
TP2CL<3>
TP2PR<3>
DISPLAY
TP2H<3>
TP2L<3>
TEST<3>
STATUS
ONLY
BIT3
ROW
TDA935X/6X/8X PS/N2 series
-
TP2CH<2>
TP2CL<2>
TP2PR<2>
DISABLE
TP2H<2>
TEST<2>
TP2L<2>
FRAME
BIT2
-
Tentative Device Specification
TP2CH<1>
TP2CL<1>
TP2PR<1>
TP2CRL<1>
TP2H<1>
TEST<1>
TP2L<1>
VPS ON
BIT1
TP2CH<0>
TP2CL<0>
TP2PR<0>
TP2CRL<0>
TP2H<0>
TP2L<0>
TEST<0>
INV ON
BIT0
RESET
00H
00H
00H
00H
00H
00H
00H
00H