XCS05XL Xilinx, XCS05XL Datasheet - Page 43

• Manufacturer Part Number: XCS05XL
• Description: Spartan and Spartan-XL Families Field Programmable Gate Arrays
• Manufacturer: Xilinx

Spartan DC Characteristics Over Operating Conditions
Spartan Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
DS060 (v1.6) September 19, 2001
Product Specification
Notes:
1.
2.
Symbol
Symbol
With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
With no output current loads, no active input pull-up resistors, all package pins at V
option.
I
I
I
V
V
T
T
V
C
CCO
RPU
RPD
I
OH
PG
SG
OL
DR
L
IN
R
High-level output voltage @ I
High-level output voltage @ I
Low-level output voltage @ I
Data retention supply voltage (below which configuration data may be lost)
Quiescent FPGA supply current
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
Pad pull-down (when selected) @ V
From pad through Primary buffer, to any clock K
From pad through Secondary buffer, to any clock K
Description
OL
OH
OH
= 12.0 mA, V
Description
(2)
= –4.0 mA, V
= –1.0 mA, V
IN
= 0V (sample tested)
IN
Spartan and Spartan-XL Families Field Programmable Gate Arrays
= 5V (sample tested)
www.xilinx.com
1-800-255-7778
CC
CC
CC
min
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
min
min
(1)
TTL outputs
CMOS outputs
TTL outputs
CMOS outputs
Commercial
Industrial
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
CC
or GND, and the FPGA configured with a Tie
Max
2.0
2.4
2.8
3.2
3.5
2.5
2.9
3.3
3.6
3.9
-4
Speed Grade
V
CC
0.02
0.02
Min
–10
2.4
3.0
-
-
-
-
-
– 0.5
Max
4.0
4.3
5.4
5.8
6.4
4.4
4.7
5.8
6.2
6.7
-3
Max
0.25
+10
0.4
0.4
3.0
6.0
10
-
-
-
-
Units
Units
mA
mA
mA
mA
pF
V
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A
43