XCS05XL Xilinx, XCS05XL Datasheet - Page 51

• Manufacturer Part Number: XCS05XL
• Description: Spartan and Spartan-XL Families Field Programmable Gate Arrays
• Manufacturer: Xilinx

Spartan IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
DS060 (v1.6) September 19, 2001
Product Specification
Notes:
1.
2.
3.
4.
Clocks
Propagation Delays - TTL Outputs
Setup and Hold Times
Global Set/Reset
Symbol
T
T
T
T
T
T
T
T
OKPOS
T
T
T
T
OKPOF
T
Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
Output timing is measured at ~50% V
rise/fall times are approximately two times longer than fast output rise/fall times.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
TSONF
TSONS
T
OKEC
T
ECOK
TSHZ
MRW
OOK
OKO
OPF
OPS
RPO
CH
CL
R
Clock High
Clock Low
Clock (OK) to Pad, fast
Clock (OK to Pad, slew-rate limited
Output (O) to Pad, fast
Output (O) to Pad, slew-rate limited
3-state to Pad High-Z (slew-rate independent)
3-state to Pad active and valid, fast
3-state to Pad active and valid, slew-rate limited
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
Minimum GSR pulse width
Delay from GSR input to any Pad
Description
(1,2)
CC
threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
Spartan and Spartan-XL Families Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values are
expressed in nanoseconds unless otherwise noted.
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
Device
XCS05
XCS10
XCS20
XCS30
XCS40
11.5
Min
3.0
3.0
2.5
0.0
2.0
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-4
Speed Grade
Max
12.0
12.5
13.0
13.5
14.0
3.3
6.9
3.6
7.2
3.0
6.0
9.6
-
-
-
-
-
-
13.5
Min
4.0
4.0
3.8
0.0
2.7
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-3
Max
15.0
15.7
16.2
16.9
17.5
4.5
7.0
4.8
7.3
3.8
7.3
9.8
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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