XCS05XL Xilinx, XCS05XL Datasheet - Page 57

• Manufacturer Part Number: XCS05XL
• Description: Spartan and Spartan-XL Families Field Programmable Gate Arrays
• Manufacturer: Xilinx

Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
DS060 (v1.6) September 19, 2001
Product Specification
Notes:
1.
DATA OUT
Write Operation
ADDRESS
WCLK (K)
DATA IN
Symbol
T
T
T
T
T
T
Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
WODS
WCDS
WPDS
WSDS
ASDS
DSDS
WE
R
T
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
Data valid after clock K
Address write cycle time (clock K period)
ILO
(1)
T
T
T
WSS
DSS
ASS
T
WOS
OLD
Dual Port RAM
T
WPS
T
T
T
NEW
AHS
WHS
DHS
Spartan and Spartan-XL Families Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
T
ILO
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-XL devices and are expressed in nano-
seconds unless otherwise noted.
DATA OUT
ADDRESS
WCLK (K)
DATA IN
Dual Port
WE
16x1
16x1
16x1
16x1
16x1
16x1
16x1
Size
T
ILO
Min
7.7
3.1
1.3
1.7
1.4
0
-
T
T
T
DSDS
ASDS
WSDS
-5
Max
T
5.2
WODS
-
-
-
-
-
-
OLD
Min
8.4
3.6
1.5
2.0
1.6
0
-
-4
T
WPDS
Max
6.1
T
T
T
-
-
-
-
-
-
NEW
WHDS
AHDS
T
DHDS
DS060_34_011300
ILO
Units
ns
ns
ns
ns
ns
ns
ns
57